Maintaining hierarchical names while doing timing simulation

[Altera_Forum]

Hi, 

 I am running post place and route (timing) simulation in ModelSim. But all the wire and register names are modified and difficult to figure.  How to maintain all the component names while doing timing simulation?  Thanks, Akshay

[Altera_Forum]

Hi Akshay, 

 You can tell the eda netlist write to maintain the hierarchy but the signal names will be weird anyhow. Use Assignments > EDA Tools Settings... > Simulation > EDA Netlist Write options > More Settings > Maintain hierarchy.  Harald

[Altera_Forum]

Harad's solution will still produce weird names, as said. The only workaround I know to get meangful signal names is to put the interesting signals on ports and propagate them up.

[Altera_Forum]

thank you for your responses..... 

 so does these signal have to be routed to the ports of the top most module? cause i cannot see the port name of even intermediate level modules?

[Altera_Forum]

Yes, to the top.

[Altera_Forum]

If you are using VHDL you can often label ifs, cases, processes, etc with a nice friendly descriptive name and then look for that name in the search and find your signals. Hope this helps a little.