I found a great one today. I tried to generate a VHDL file from a GDF file.The tool reports the following: Warning (275017): Component "FIFO_192" is not instantiated in the "VHDL" design because none of its input ports or output ports are connected. What makes this interesting is that the part has been in there for 3 years and this is the first time the tool complained. Also, it really wants the lines of code for the part. I added them manually and it works fine. This is a major tool bug that Altera/Intel needs to fix. I'm sire they will fix it in the next release. NOT!