Make DE0 Nano to be Bootable and use SDRAM to store hardware and software

[Altera_Forum]

Hi all, Please help me, I have been stuck with this problem for MONTHS. 

 I am currently working on a Nios II based design using the DE0-Nano board and the on board 32Mb sdram. My system is as follows:  Windows 10 Quarts V.14.1 Qsys system: - 50MHz CLK - CPU - EPCS Flash Controller - Onchip memory - PIO - SDRAM controller - JTAG UART - SysID - UART - PIO  Reset and exception vectors have been set to EPCS Flash Controller and SDRAM Controller. SDRAM is clocked by separated PLL and I have confirmed that the SDRAM works without any problem.  Now I am at the point where I want to load the hardware design and software onto the EPCS so the board can operate in a standalone situation. For more information, I am using a lot of libraries and not using the small c option. So, I need to use SDRAM to store instructions and data for NIOS application. I mention this because the method of programming a bootable system in the de0 nano literature (initializing on-chip memory with program code) is not an option due to the size of my code. I've looked through many posts in the internet regarding this topic. There's a lot of outdated documentation and conflicting forum posts about this process so I was hoping someone could lend me some guidance.  As stated above, there are various information on the internet so I have tried two methods.  The first method is to convert .sof file into .jic file. Based on this method, I can make the hardware to be bootable easily. Then I tried to make the software to be loaded by the method in the below link.  http://geobyjmhembeddedengineer.blogspot.co.uk/2014/06/executing-code-on-nios-ii-directly.html  I can program the .jic file into the board. The hardware becomes bootable but the software does not load after the board reset. It caused me to doubt that whether this first method can not be used together with SDRAM so I tried the second method.  In the second method, I added EPCS Flash Controller. Set Reset and exception vectors to EPCS Flash Controller and Onchip Memory. I have done everything that is described here.  https://sites.google.com/site/fpgaandco/niosii-standalone  But the result is error message when I try t do the flash programming as shown below.  https://dl.dropboxusercontent.com/u/153995/error.png  According to many threads, this error is caused by the new Scansion chip in the board and can be solved by adding a patch file into the bin directory in nios2eds folder. I have done it but the error still appears.  I am very confuse now. Sorry for my noobness. Hope someone can help me, please. Thank you in advanced.  You can download my project from here.  https://dl.dropboxusercontent.com/u/153995/20160626%20project_work_sdram_and_led_0.01s_yossiri.zip  Could you try it whether it is work on your computer?

[Altera_Forum]

For more information, I just tried the second method on Windows 7. I just tried to do it on drive C instead of drive Z as well but the error still appears :-(

[Altera_Forum]

Someone help me please T_T

[Altera_Forum]

I edited the post so that it can be more clearly to be understood.

[Altera_Forum]

What does your 'patch file' contain? 

 Putting the attached 'nios2-flash-override.txt' into your ../nios2eds/bin' folder should fix things.  Cheers, Alex

[Altera_Forum]

--- Quote Start ---  What does your 'patch file' contain?  Putting the attached 'nios2-flash-override.txt' into your ../nios2eds/bin' folder should fix things.  Cheers, Alex  --- Quote End ---    Thank you very much Alex. Content in the patch file in the CD comes with the board is shown below. It differ from the one you uploaded.  [EPCS-010216]# EPCS64N(lead-free) sector_size = 65536 sector_count = 128  However, I also tried your patch file but the flash programmer still have the same problem.  If you have a DE0 Nano board. Could you download my project and do the flash programmer with your board, please? The download link is works.  https://dl.dropboxusercontent.com/u/153995/20160626%20project_work_sdram_and_led_0.01s_yossiri.zip  I have stuck with this problem for a very long time. I bough many books, read them, also read many treads. I tried all the ways but still cannot solve. :-(

[Altera_Forum]

It isn't clear from your description, but when you're using the .jic you also need to have added the EPCS Flash Controller and have configured the NIOS to boot from the EPCS bootloader. In other words, just programming the .jic file isn't enough to make your software get copied to SDRAM after reset. In your shoes, I would revisit the .jic method after having changed your hardware to use the EPCS boot method. 

 Whats happening here is that the EPCS ROM bootloader is just a simple program for the NIOS that knows how to point back to the EPCS flash and copy the contents after the hardware section to the locations encoded in the .jic  Here are some Altera links, AN736 in particular:  https://www.altera.com/support/support-resources/knowledge-base/solutions/rd12092009_471.html https://www.altera.com/en_us/pdfs/literature/an/an736.pdf https://www.altera.com/en_us/pdfs/literature/an/an458.pdf

[Altera_Forum]

--- Quote Start ---  It isn't clear from your description, but when you're using the .jic you also need to have added the EPCS Flash Controller and have configured the NIOS to boot from the EPCS bootloader. In other words, just programming the .jic file isn't enough to make your software get copied to SDRAM after reset. In your shoes, I would revisit the .jic method after having changed your hardware to use the EPCS boot method.  Whats happening here is that the EPCS ROM bootloader is just a simple program for the NIOS that knows how to point back to the EPCS flash and copy the contents after the hardware section to the locations encoded in the .jic  Here are some Altera links, AN736 in particular:  https://www.altera.com/support/support-resources/knowledge-base/solutions/rd12092009_471.html https://www.altera.com/en_us/pdfs/literature/an/an736.pdf https://www.altera.com/en_us/pdfs/literature/an/an458.pdf  --- Quote End ---     Thank you ted. What is not clear from my description? I already have EPCS Flash Controller in my Nios.  I have already configure the Nios to boot from the EPCS Memory.a  But I don't know about bootloader program. It is not described in the formal document below :( ftp://ftp.altera.com/up/pub/altera_material/15.0/tutorials/de0-nano/using_de0-nano_flash.pdf  Now I am comprehending your three documents.

[Altera_Forum]

Hello ted, 

 I contacted Terasic. Today they informed me that they tried to do the flash programmer to load my project onto their DE0 Nano board as I requested. And they can do it without any problem. I don't understand that why I cannot do it. I have tried with two of my boards.  Another method is to try to create a jic file then program it onto the board. I also have done it. Today I found something very STRANGE! I found that after I program the jic file onto the board, the hardware configuration is bootable. Then, two minutes later the software is booted. you can see it here. https://youtu.be/hfsh4ifk_yk At last the software became bootable. BUT WHY IT NEEDS TWO MINUTES???

[Altera_Forum]

I have finally solved the problem. By changing to Windows 7 and Qusrtus 13.1. Thanks Altera!!!