Manually applied Clock Data Recovery in Arria II GX

[Altera_Forum]

I have a unique design that works on CoaXpress interface. This design is specifically for the Low Speed return interface on any given channel (20.8 Mbps max). We chose to use the high speed gigabit protocol over this interface, even though it was so slow. In doing so, I created my own serializer and deserializer, and I'm using them with 8b/10b encoder/decoder IP (I had to do this because any IP that did the serialization/deserialization was ONLY for high speed [gigabit] applications and differential signals were required at the pins of the device - CoaXpress Low speed is single sided and therefore cannot use differential signaling).  

 Anyway, I have the interfaces working (same device looped back externally with same clocks), but not across two mutually exclusive platforms. So I need to recover the clock on the receive side to make this work.  Can anyone tell me what primitives/macros I would instantiate to just get the CDR integrated in my system so I can recover the clock from my 8b/10b encoded data? OR if there's another method that I can use discrete PLLs and whatever to do it myself that would be beneficial if I could see the code around it...  Thanks

[Altera_Forum]

Hi, 

 To use the CDR of the transceiver channel, you would need to instantiate ALTGX instance to access and control the transceiver blocks including CDR. By the way, if I remember it correctly, the minimum data rate supported by Arria II GX transceiver is ~600Mbps which is much higher that your 20.8Mbps. You might want to try using oversampling to meet the transceiver minimum data rate. Also, the CDR is design to work with differential signaling. You would need to perform hardware to verify if the CDR can work with your single ended signaling.

[Altera_Forum]

Maybe you can reuse the RX oversampling module and the Create_Recoverd_Clock parts of this design posted on Altera Wiki. 

http://www.alterawiki.com/wiki/file:gxiv_siboard_1ch_multi_prbs_155mbps_clock_recovery.zip

[Altera_Forum]

Thanks for the responses, I will take both into consideration. I appreciate the tips, I may check back with more questions.

[Altera_Forum]

A quick update to my problem. Thanks again bfkstimchan and kkaibara, I didn't get far with the GX approach, but I did have some success with my problem. I basically abandoned all hope of any IP solution and decided to make my own clock recovery circuit. I had an idea in mind which I found an almost exact match for with this guy's post.  

 http://www.twyman.org.uk/clock_recovery/  His approach seemed fairly sound for a slow recovery circuit so I implemented it and have found it to work. The one thing I will add for Altera users is I would advise using primitives for each element of the edges detector. As in, go instantiate DFF using the actual primitive instead of inferring through VHDL code. Same thing with the inverters - Actually instantiate an lpm_inv for each one.   Then you have to generate a clock out of the sample[2] bit. The LPM_COUNTER, if you push down into it has flip flops at the outputs, so you can use the q of those to generate yyour recovered clock. As it was, here was my .sdf file entry to generate my recovered clock.  create_generated_clock -name CDR_Recovered_clk -source [get_pins {slow_clock|altpll_component|auto_generated|pll1|clk[3]}]   -divide_by 16 [get_pins {Inst_LS_XCVR_RX|\PLL_saver:CDR_DIG|sample_count|auto_generated|counter_reg_bit[3]|q}]  Note: My oversampling clock for the digital CDR circuit was 16x the expected recovered clock. In the design reference that I posted above, he uses an 8x clock - I just wanted higher resolution. Therefore my recovered clock bit was [3] instead of [2]. And I had to tell it divide by 16 from my oversampling clock  Therefore, Oversamplign clock was 320Mhz, and my recovered clock was 20Mhz.   Works well!