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Altera_Forum
Honored Contributor I
2,266 Views

Marvell 88EE1111 PHY tranciever MDIO reg configuration

I'm trying to troubleshoot PHY for my dual Ethernet design on the DE2-115 Cyclone IV board. (I have to load my *.elf file twice for some reason for my design to work).  

 

In trying to figure out what's I notice that the DE2-115 uses the Marvell 88EE1111 PHY Tranciever chip. As per IEEE 802.3 2015, MDIO registers 0-15 are standard, but 16-31 are manufacture dependent. Does anyone have any leads on configuring Marvell 88EE1111? The "datasheet" on their website is only a product brief and does not describe what the registers do. 

 

 

I noticed in an excerpt from the Altera University TSE example (below), register 20 is written to in order to set up delay for input/output clk, but neither Altera nor Marvell provide any further information on why they chose this value or what it means. 

// Write to register 20 of the PHY chip for Ethernet port 2 to set up delay for input/output clk *(tse + 0xB4) = *(tse + 0xB4) | 0x0082;
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31 Replies
Altera_Forum
Honored Contributor I
414 Views

A full copy of the Marvell datasheet comes on the DE2-115 CD, which can also be downloaded from Terasic's website. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
414 Views

Thanks Alex. The document seems to be the same as their website and contains pin-out information (nothing about configuration registers). Some of their other products do, but some seem to be undocumented. I know that Reg 16 is for automatic crossover and Reg 20 is delay for the input/output clock.

Altera_Forum
Honored Contributor I
414 Views

All,  

As an update, I received an email from their sales team. It seems they only provide them with companies going into volume production: 

 

"Typically Marvell will only engage with customers that are building a product that will go into volume production. A NDA is required in order to get detailed data sheets. They do not engage with Universities or private individuals."
Altera_Forum
Honored Contributor I
414 Views

Indeed - my mistake. I found only the product brief shipped with the kit. 

 

Going back to your original issue - does your code allow the Phy time to 'settle' before trying to configure it? By the time you re-load the elf it's been running for a number of seconds. Are you simply trying to do 'something' too early? 

 

Do you write to address 20 in your code? Comment it out if so. I doubt it's relevant. I remember not having to do any configuration to get the Phy working. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
414 Views

Hello Jsag, 

 

I ran into a similar problem and I have working application with ethernet on the DE2-115 that i can share and some usefull info. 

 

Best Regards, 

Johi.
Altera_Forum
Honored Contributor I
414 Views

Johi, that would be great! I would appreciate. How would you send? 

 

Best, 

Jsag
Altera_Forum
Honored Contributor I
414 Views

 

--- Quote Start ---  

Indeed - my mistake. I found only the product brief shipped with the kit. 

 

Going back to your original issue - does your code allow the Phy time to 'settle' before trying to configure it? By the time you re-load the elf it's been running for a number of seconds. Are you simply trying to do 'something' too early? 

 

Do you write to address 20 in your code? Comment it out if so. I doubt it's relevant. I remember not having to do any configuration to get the Phy working. 

 

Cheers, 

Alex 

--- Quote End ---  

 

 

Alex, i'm not sure why, but it seems MDIO register 20 for setting up the delay for the I/O clock for Gigabit DDIO seems necessary in my case. I tried removing the line, but transmission seems to stop. Only when it is enabled does the traffic resume.
Altera_Forum
Honored Contributor I
414 Views

Hello Jsag, 

 

I think we could create a private channel to exchange the info you need, skype, mail, what is your proposition? 

I thought we could send private messages over the forum, but the admin has disabled mine, can you ? 

 

Best Regards, 

Johi.
Altera_Forum
Honored Contributor I
414 Views

I've found my Marvell datasheet. See the attached snippets of it that cover Address 20. There's also a timing diagram to show the impact of the bits being changed by your code. It seems to contradict my original statement about "not having to do any configuration to get the Phy working." Clearly a little too long ago for my grey matter to cope with... 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
414 Views

Alex, 

 

Thanks! It seems the register is important of use with a DDIO for RX/TX delays. And for line loopbacks for testing. I thought it was for setting a delay value rather than binary on/off. 

 

I did find the reason for my needing to load twice. I wasn't configuring the PHY address within the Altera TSE MAC Megacore prior to configuring the Marvel 88EE1111 PHY (addresses 0x10 and 0x11 for DE2-115). Therefore, all my first-load configurations went to some imaginary PHY at default MDIO address 0x00. Since I was setting the correct MDIO PHY address at the end, the second-load configurations would be send to the correct address. Thus, I was require two loads of the *.elf file in order to get my design working. I simply set the PHY address first to fix the problem. Rookie mistake that took me two months to debug. 

 

(Johi, thank you as well!)
Altera_Forum
Honored Contributor I
414 Views

JSAG, 

 

I think i had a similar or identical problem with my board some months ago. 

 

It had to do with forgetting to reset the PHY after startup. 

 

Look in tse.c in project file attached (It is a project i am working on to provide a basic ethernet sniffer for the DEII that can send ARP and UDP and can receive ARP en UDP in a small fixed ethernet adress configuration).  

 

Best Regards, 

Johi.
Altera_Forum
Honored Contributor I
414 Views

Hello! 

Do you have your design working? I tried 88E1111 with Cyclone IV with GMII interface and the only result I have is correct RX (I see that in Signal Tap) and line loopback. All my attempts to transmit data is out of luck, internal loopback also keep silence. How to manage TX clocks? I suspect my problem in TX clocks - do you use PLL to generate TX clock with shifted phase? 

Sorry for offtopic.
Altera_Forum
Honored Contributor I
414 Views

FPGA, 

 

To remove line loopback and ensure both TX and RX delays for the DDIO clock are set, be sure to set the 88EE1111 register 20 to 0x0082. Bit 14 controls line loopback. Bits 15 and 1 are RX/TX delay. 

 

I do have PLL and DDIO modules instantiated at the toplevel, apart from my Nios II system. The best way to describe it would be to reference the excelent tutorial for the TSE on the DE2-115 (can be found at https://www.altera.com/support/training/university/materials-tutorials.html). Page 21 has a typo (Ethernet port 2 does not exist. It should read "Ethernet port 1"). It includes commands needed to set up auto-negotiation and the GMII transmit speed as well. 

 

I hope that works! 

 

For further development, I would definitely recommend the UDP Offload Example at AlteraWiki!
Altera_Forum
Honored Contributor I
414 Views

Alex, 

 

Any chance of posting the full data sheet? I'm trying to put the 88E1111 on a Max 10 Development kit in 10/100 mode via MII.
Altera_Forum
Honored Contributor I
414 Views

Hello Corestar, 

I know where to find what you need. 

Are you on skype ? 

Best Regards, 

Johi.
Altera_Forum
Honored Contributor I
414 Views

Hi Johi, 

 

I don't have easy access to Skype. Is it something you could post? I'm trying to setup the Max 10 Devel Kit using the "small" 10/100 EMAC mode which uses MII only. All the examples are for Gigabit and the full EMAC and it is not clear how to change it without the Phy datasheet.  

 

Very frustrating that Marvell makes it difficult to use their chip. Open letter to vendors (I'm sure this will cause them to take immediate action :-).  

 

Dear Devel Board Vendors,  

 

Please stop using chips from customer HOSTILE vendors like Marvell that seem to think it is a good idea to make life miserable for anyone wanting to buy their products. Many of us tend to use the same chips as the devel board on our own custom boards but cannot do so with a hostile vendor like Marvell.
Altera_Forum
Honored Contributor I
414 Views

 

--- Quote Start ---  

I've found my Marvell datasheet. See the attached snippets of it that cover Address 20. There's also a timing diagram to show the impact of the bits being changed by your code. It seems to contradict my original statement about "not having to do any configuration to get the Phy working." Clearly a little too long ago for my grey matter to cope with... 

 

Cheers, 

Alex 

--- Quote End ---  

 

 

Hi Alex, 

 

Can you tell me where you found the information of the control register of Marvell 88E1111 PHY chips? Thanks! 

 

Regards, 

Minyan
Altera_Forum
Honored Contributor I
414 Views

All the info is in the complete datasheet for the device. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
414 Views

If you go to the Marvell Phy page, there is a "Contact Sales" link on the right. You have to sign an NDA and assure them you do not plan to conquer planet earth using their Phy and they will then send links to download it. 

 

 

https://www.marvell.com/transceivers/alaska-gbe/ (https://www.marvell.com/transceivers/alaska-gbe/

 

If you are not locked into this chip, there are better choices out there.
Altera_Forum
Honored Contributor I
64 Views

Hello, I need some help. 

I have an altera DE-115 which has two ethernet ports, all i want is to receive ethernet frame on ethernet port 1 and send that same frame from ethernet port 0. I can receive ethernet frame on fpga board from ethernet port 1 but cannot transmit that same frame from ethernet port 0. On both ports two different PC's are connected. 

 

What changes should i make in this code 

 

volatile int * tse = (int *) 0x00102000; 

 

Initialize the MAC address 

*(tse + 3) = 0x116E6001; 

*(tse + 4) = 0x00000F02; 

 

// Specify the addresses of the PHY devices to be accessed through MDIO interface 

*(tse + 0x0F) = 0x10; 

*(tse + 0x10) = 0x11; 

 

Write to register 20 of the PHY chip for Ethernet port 0 to set up line loopback 

*(tse + 0x94) = 0x4000; 

 

// Write to register 16 of the PHY chip for Ethernet port 1 to enable automatic crossover for all modes("| = OR") 

*(tse + 0xB0) = *(tse + 0xB0) | 0x0060; 

 

// Write to register 20 of the PHY chip for Ethernet port 2 to set up delay for input/output clk 

*(tse + 0xB4) = *(tse + 0xB4) | 0x0082; 

 

// Software reset the second PHY chip and wait 

*(tse + 0xA0) = *(tse + 0xA0) | 0x8000; 

while ( *(tse + 0xA0) & 0x8000 ) 

 

 

// Enable read and write transfers, gigabit Ethernet operation, and CRC forwarding 

*(tse + 2) = *(tse + 2) | 0x0000004B;
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