Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21611 Discussions

Matching Xilinx Parallel bit format

Altera_Forum
Honored Contributor II
‎08-11-2009 02:23 PM
1,203 Views

I have a contract that has been using Xilinx for a long time. They parallel load the FPGA's by taking the Xilinx HEX formated code and storing it on their system (not Intel HEX format with all the line numbers, semi-colons checksums, etc - just the payload), then read the HEX file and convert it to true binary before putting it out on the 8 I/O lines. 

 

It is not clear which format from the Altera tools will get me closest to the same format and rather then just experiment until I get it right, I thought I would ask here in case someone has already worked all that out. 

 

Thanks, 

Avatar
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.