any document about chip planner?

[Altera_Forum]

I am using Quartus8.1. in chip planner, if you use show delays to check route delay, you will have two number like "R:xxxns, F:xxxns" 

what does this mean. I need learn more detail about use chip planner. any good document?   Thanks.

[Altera_Forum]

Rise and Fall. I personally always turn this off. It clutters the view and I can get a better analysis in TimeQuest. (Chip Planner still good for visualizing why TimeQuest's numbers are what they are.) Not sure about documentation, as I've just learned playing with it. What is it you're trying to do?

[Altera_Forum]

Just to clarify, note that there are "sub-models" beyond this. For example, the exact same path will have a slightly different delay in the same timing model depending on if you're doing a setup analysis or hold analysis. This accounts for On-Die Variation(amongst other things). A graphical tool can't really show all this. TimeQuest is the place to get the numbers. 

Two things I use that aren't always obvious: 1) Go to TimeQuest and report a number of failing paths. Highligt a column of them all(doesn't matter which one) and right-click Locate Path -> Chip Planner. In essence you use TimeQuest's report_timing to craft the paths you want to look at and view them in the Chip Planner. 2) If you're doing Incremental Compilation, the Partition Planner task view(top-right pull-down) shows a different color for each one. But you don't have to do IC to see this. First launch the Tools -> Design Partition Planner. Grab a large hierarchy, right-click and Extract from Parent. Note that this does absolutely nothing to the design, it just helps you visualize it in this tool. Once you've done that to a few hierarchies, launch Chip Planner(both windows open) and go to the Partition Planner view. All the hierarchies you extracted should now be color coded. It's not overly useful, but helps me visualize where the fitter puts things, which is interesting to begin with, and comes in handy if floorplanning or anything like that.

[Altera_Forum]

thanks for explain this. I used to use classic timing analysis tools. in this Timequest, after I got a clock network delay, sometimes I want check how this network are routed. and how the delays are distributed. if the delay calculated by chip planner and Timequest are not match. I won't feel very confident about the timequest analysis result. I am very glad to know you.

[Altera_Forum]

They will be very close, but it will always be because Chip Planner doesn't have enough info. Always rely on TimeQuest to determine if you meet timing. You mention clock network delay. When you want more info, be sure to run report_timing with "-detail full_path", so the clock network delay is broken out in detail. I am in the habit of looking at the X/Y locations in TimeQuest and not using Chip Planner at all, but I understand that is not overly intuitive and will use Chip Planner just for a nice visual.

[Altera_Forum]

I will try this "-detail full_path", thanks.