Max 10 Open Drain in analog banks

[Altera_Forum]

Hello, 

 I've got a board with a 10M08SCU (no ADC) on it. I'm trying to use banks 1A and 1B to control PMOS high-side drivers. The output pin from the Max 10 is connected to the gate and pulled up to 5v. On all of the lines I have connected in this way, only the lines in 1A aren't working as I expected. 3.3v lines driven by open-drain GPIO in 1A function the same as those in other banks as well. The 5v lines don't allow the line to rise all the way to 5v (usually these lines are 4-4.2v), resulting in a permanently semi-on high-side driver.  My HDL is identical for all of these different ports, and I've verified that the port is not driving the rail when it's de-asserted. It seems like maybe there's a clamp diode in there that I'm not aware of. All of the PCI clamps have been explicitly disabled in the assignment editor. This is happening across several boards, and the two offending lines are direct and only routed ~.25" on an internal layer. My 5v pull-up supply measures good at the device as well. I've even removed a resistor to look at the voltage of the output pin, and it was a few hundred mV when de-asserted, and 0v when asserted, which seem like reasonable values for an open-drain line not pulled up.  I haven't been able to find anything concrete about using these banks for digital I/O, nor how they differ when there are no ADCs in the package, so I'm kind of at a loss as to what's happening here. From what I've read, it sounds like if any pins are used for analog, then GPIO is not available on the analog I/O banks, but I've also heard that's not enforced by Quartus. I don't have any ADCs, so it seems to me like this ought to work. I am using a PLL, but I didn't see anywhere where that was at odds with using 1a/b for GPIO.  So as far as I can tell, this should be working, but I must be missing something. Does anyone know what my problem is, or have suggestions about how to address it?  Thanks, Ben

[Altera_Forum]

4-4.2V sounds very like protection diodes kicking in. 

 You can look at the guidelines for enabling/disabling clamp diodes - page 3-2 of the "max 10 general purpose i/o user guide (max 10 general purpose i/o user guide)". You can potentially disable them.  However...  Which MAX 10 document have found that states you can use the I/O of MAX 10 directly as open drain operating at 5V?  Refer to Table 2-4, on page 2-14 of the same "MAX 10 General Purpose I/O User Guide". The 'Open Drain' row states the I/O standards MAX 10 supports. There's nothing about operating at 5V.  There's also the 'Maximum Allowed Overshoot' table in the "max 10 fpga device datasheet (https://www.altera.com/en_us/pdfs/literature/hb/max-10/m10_datasheet.pdf)". You can over-drive a pin to 4.12V indefinitely, but not much higher without risking damage to the device.  You really need an external fet...  Cheers, Alex

[Altera_Forum]

Thanks for the response. I guess I should have paid more attention to the datasheet. Based on the sections you referenced in the datasheet, I should expect a failure on my other lines in just a few days (maybe a couple weeks at best) of on time, which is the idle state for these lines. 

 I thought I'd be able to get away with this since I was driving them open drain, but as you mentioned, there aren't any apparent mentions of 5v in the datasheet. Unfortunately, I'm very constrained on space with this board, so I'd really like to be able to not include that external FET, and it'd be nice to be able to test on this rev with all of my hardware. Is there anything I can do to mitigate this on my current hardware, and without adding that external FET on my next rev?

[Altera_Forum]

For the purposes of testing, can you drop your 5V rail to 4V? 

 The extra FET you need needn't be large - an SOT23 or SC70 or smaller would be perfectly adequate.  Cheers, Alex

[Altera_Forum]

One option is to use integrated load switches that can work with 2.5 or 3.3 V logic control. The other using little HCT or similar logic gates as 3.3 to 5V level converter.

[Altera_Forum]

Thanks for the responses, fellas. I appreciate the help. I guess I'll have to go with the gate FETs on the next rev (I'll look at the compatible drivers too, but for size/cost, I don't think I'm going to find what I need). At least I'll be able to see how these guys fare in the mean time. Interesting information for hacky future endeavors, if nothing else. 

 If anyone else stumbles across this thread, I'd still be interested in your take, so don't be shy!  Thanks again, Ben