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Max 10 Pin Compatibility

F_P_G_A
Beginner
346 Views

Hello Community,

I can use in my design either 10M04DCF256A7G or 10M08DCF256A7G. They are pin compatible. But what if I want to use the other members of the family like 10M16DCF256A7G, 10M25DCF256A7G or 10M50DCF256A7G in the same design. Are they still pin compatible? According to the datasheet there are 3 pins that are different. In case of 10M04DCF256A7G and 10M08DCF256A7G they are unconnected hence my design has no connections at these pins. The other family members has connections/functionalities at these pins. But what happens if they are unconnected?

P.S.: 

- 10M04DCF256A7G and10M08DCF256A7G are just unavailable. I need to find other solutions.

- I need 4000-6000 devices per month. 

 

 

Thanks a lot for the answers!

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Fakhrul
Employee
257 Views

Hi FPGA,


As long as they fall under the same package it shouldn't be a problem.

You can refer to the Migration Capability Across Intel MAX 10 Devices on page 8 in the following document:


Intel® MAX® 10 FPGA Device Overview


Regards,

Fakhrul



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4 Replies
Fakhrul
Employee
258 Views

Hi FPGA,


As long as they fall under the same package it shouldn't be a problem.

You can refer to the Migration Capability Across Intel MAX 10 Devices on page 8 in the following document:


Intel® MAX® 10 FPGA Device Overview


Regards,

Fakhrul



Fakhrul
Employee
212 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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FvM
Valued Contributor II
204 Views

Hello,
to be sure not to overlook any necessary connection in migration compatible devices, I'd proceed as follows

- select all intended migration devices in your Quartus design
- place a top level entity with all port signals and signal direction

- optionally add basic functionality for dedicated signals (PLLs connecting to clock in- and outputs, SERDES IP)
- assign locations and IO-standards for all signals
- compile the design

- review the required connection in generate .pin file. You particulary find all pins needing connection to GND or supply voltage for migration devices

 

Regards

Frank

Fakhrul
Employee
126 Views

Hi FvM,

 

As long as there's no error nor significant warning during the compilation process, plus with all your mentioned procedures above, it should be no issue.

 

Regards,

Fakhrul

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