Max 10 dac output

Altera_Forum · ‎03-21-2018

Hey everyone,

I'm trying to check if the DAC_SMA connector is working with the code below.

i compiled it and programmed on the max10 board, but when i connected it to an external scope I see nothing.

what could be the reason?

i simulated it with modelsim and the time constraints of the DAC8551 and the code are met.

from my understanding the scope should show steady voltage level.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY try IS
PORT(USER_PB:IN STD_LOGIC_vector(0 downto 0);
		CLK_10_ADC:IN STD_LOGIC;
		SYNC:OUT STD_LOGIC;
		SCLK:OUT STD_LOGIC;
		DIN:OUT STD_LOGIC;
		USER_LED:OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
		--USER_LED:OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
		);
END;
ARCHITECTURE try OF try IS
SIGNAL SYS_CLK: STD_LOGIC;
SIGNAL ST:STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL RDATA:STD_LOGIC_VECTOR(23 DOWNTO 0);
SIGNAL CNT:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL DATA:STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
DATA<="1111111111111111";
PROCESS(USER_PB,CLK_10_ADC)
BEGIN
	IF(user_pb(0)='0')THEN
		ST<="000";
		USER_LED<="000";
		SYNC<='1';
		SCLK<='0';
		DIN<='0';
		CNT<="00000000";
		ELSIF(CLK_10_ADC='1' AND CLK_10_ADC'EVENT)THEN
				USER_LED<=NOT(ST);
				CASE ST IS
						WHEN "000"=>
							SCLK  <='0';
							RDATA(23 DOWNTO 0)<="00000011"&DATA; 
							SYNC  <='0'; 
							ST<= "001"; 
							--USER_LED<= "110" ;
						WHEN "001"=>
							SCLK  <='1';
							RDATA(23 DOWNTO 0)<=RDATA(22 DOWNTO 0)&'0'; 
							DIN<=RDATA(23);
							SYNC  <='0'; 
							ST<= "010";
							--USER_LED<= "101"	;
						WHEN "010"=>
							CNT <= CNT +'1'; 
							ST<= "011";
							--USER_LED<= "100";
							SCLK  <='0' ;
							IF(CNT=24)THEN
								ST<="100";
								--USER_LED<= "011";
								CNT<="00000000";
								SYNC<='1';
							ELSE
								ST<="001";
								--USER_LED<= "110";
							END IF;
						WHEN "100"=>
							IF (CNT=4)THEN
								CNT<="00000000";
								ST<="000" ;
								--USER_LED<= "000";			
								DIN   <='0' ;
							ELSE
								CNT<=CNT+'1';
							END IF;
						WHEN OTHERS=>
							NULL;
				END CASE;
		END IF;
	END PROCESS;
END ARCHITECTURE;

Altera_Forum · ‎03-22-2018

Hi,

Have checked clock being generated and pin assignments?

Use the signal tap to debug.

Let me know if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

Altera_Forum · ‎03-22-2018

Your code is a bit hard to read due to formatting. But in state "000" you have:


RDATA(23 DOWNTO 0)<="00000011"&DATA;

which as I read the DAC8551 data sheet "7.4.1 Power-Down Modes" puts the DAC in High-Z mode. You probably want normal operation (ie "00" instead of "11" for bits 17 and 16). Also, it looks like the DIN is transferred on the falling edge of SCLK, not the rising edge.

Note, most people would use an enumerated type for the state instead of a std_logic_vector. If you really want to output it to the USER_LED, there is a convoluted way to convert the state to a std_logic_vector, but you won't see anything at this speed anyway.

You have many things in the registered proc that should probably be in combinational logic. This makes it much simpler to see what the outputs are in a given state. For example, just drive DIN using:


    DIN <= RDATA(23) when SYNC = '0' else '0';

outside the process. Same for the other outputs of the state machine (ie SCLK and SYNC). The way you have it now, you have to remember that the changes do not take effect until the next clock cycle.

Many people would use two processes for the state machine instead of combinational logic as I've suggested.

There are many other issues with the code, but hope this helps as a start.