Max 10 performance degradation of ADC when ignoring I/O usage restriction

[SRode1]

The GPIO User Guide states only about 40% of the I/Os are available when using the internal ADC of the MAX 10 in E144 package with I/O voltage of 3.3V. Quartus states that the pin placement will cause performance degradation on ADC sampling. Since I would like to use the leaded E144 package and need nearly all I/O pins for the design, I am interested which performance I can still expect when ignoring the pin placement notes. And which restrictions should be followed for I/Os (speeds, drive strength) in that case?

[ShafiqY_Intel]

Hi SRode1,

For package E144:

• Cannot be used as GPIO pins = Bank 1A, 1B, 2, and 8
• Can be used as GPIO pins = Banks 4 and 6
• Can be used as a percentage of GPIO pins = Banks 3(39%), 5(83%), and 7(39%)

Since you are using voltage of 3.3V, your I/O standard is in Group 4.

Therefore, the percentage of GPIO pins allowed is Bank 3(39%), Bank 5(83%), and Bank 7(39%).

Noted:  The Intel Quartus Prime software will issue a critical warning if this I/O settings violated.

Thanks