Max II CPLD design failing at low temperatures

[Altera_Forum]

I have a design that uses an industrial temperature Max II (EPM2210GF256I5). The design is very simple. It does some serial pass-through at 115,200 baud and some at a higher rate (16 x 64kHz). The master clock is just under 20MHz. If I put the board in an environmental chamber, it works fine at high temperatures, but on some devices the design begins to fail at around -10C. If I put an older version of the design in the same device, it works find down to -20C. 

 Does anyone know of any relevant application notes or have any suggestions on what to look into?  Many thanks,  -Michael

[Altera_Forum]

Hi, 

 typical behaviour if your design is not FULLY synchronous :D   Hope this help.

[Altera_Forum]

Michael,  

 my bet would be that you're generating slower clocks from your 20MHz clock and that you're experiencing the effect of hold time time violations due to clock skew.  First, I suggest you use TimeQuest with multi-corner analysis enabled, which should report that your design will fail for the fast timming model.  Second, the following topic has a good explanation of the issues that arise with ripple clocks and alternative solutions  http://alteraforums.com/forum/showthread.php?t=2388