How to debug a cpld?

[Altera_Forum]

Hello. I'm moving my first steps with cpld design. I put an EPM7064AELC441 on a breadboard, wrote some verilog code (through Quartus) and saw a led flashing. 

To continue, some form of debugging is needed. My question: is JTAG the way to see some internal state? With which software? Or should I buy a logic analyzer?  Thanks a lot, any help is really appreciated Enrico

[Altera_Forum]

I am not sure if using JTAG port is the current trend for cplds. If you don't want to buy logic analyser then use plenty of LEDs with several flashing rates 

or use fpga platform to debug cpld code

[Altera_Forum]

> or use fpga platform to debug cpld code 

This is an interesting hint. What kind of debugging tools are available with fpga? I read something about debug core, multiplexers, etc.

[Altera_Forum]

The debugging options with simple CPLD (e.g. MAX 7000) are limited to JTAG boundary scan. Various third party tools are available for it, e.g. TopJTAG, that's said to support Altera programming adapters. http://www.topjtag.com/probe/ 

 With Altera FPGA, you have powerful debugging tools, particularly SignalTap II, that acquires internal signals in real time. And all tools for free.