Re: Max V I2C hardware connection

HWEngineer · ‎03-14-2022

I am implementing I2C slaves on Max V to for reading of registers.

1) Can the I2C be connected to any I/O pins?

2) The master is a I2C, 5V. The handbook mentioned that Max V can be 5V tolerant with an external resistors and clamped diode. Is there any reference design for this? If not, is it a voltage divider resistors to provide 3.3V to Max V?

AminT_Intel · ‎03-17-2022

Hello,

Max V does not have dedicated I2C slaves. If you'd like to use it, you will have to develop controller inside of the FPGA. As for reference design, you can refer to Intel® FPGA Design Examples if we have reference design of it.

Thanks.

HWEngineer · ‎03-17-2022

The question is more on the hardware connection of the MaxV as the handbook does not have any informtaion on the following:

1) Can the I2C be connected to any I/O pins?

2) The master is a I2C, 5V. The handbook mentioned that Max V can be 5V tolerant with an external resistors and clamped diode. Is there any reference design for this? If not, is it a voltage divider resistors to provide 3.3V to Max V? I managed to find the application note for the 5V tolerant. Is there any recommended external clamping diode?

AminT_Intel · ‎03-18-2022

Hello,

I think I have answered this on my previous response. Can you elaborate your concern?

Thank you.

HWEngineer · ‎03-20-2022

You mentioned "Max V does not have dedicated I2C slaves. If you'd like to use it, you will have to develop controller inside of the FPGA." But that does not answer if I2C can be connected electrically to any of the I/O pins. When I said connect electrically, I mean the physical pin of MaxV. Can MaxV I/O pin be connected directly to an I2C or does it need an external I2C to LVTTL translator?

AminT_Intel · ‎03-24-2022

Hello,

From my last post, developing a controller meaning writing an RTL for that. Once you have done that, the pins should be connected with right IO standard according to the Max V datasheet.

Thank you

AminT_Intel · ‎03-31-2022

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