Max V JTAG Daisy Chain

[Altera_Forum]

I'm implementing a JTAG Daisy Chain for the first time on a PCB. Previously, on a prototype board I had two headers for JTAG programming but I'd like to utilize a daisy-chain configuration to reduce space now. 

 Here's how my JTAG header looks like:  http://i.imgur.com/WjWCc.jpg   This is pretty standard. Here's how my JTAG daisy chain looks like, based on App. Note 100:  http://i.imgur.com/2Y3dQ.jpg   I'm posting this here incase there any issues that I need to be aware of. This is a stupid question but I had to ask: I assume when I try to program the devices I'll see a list of devices in the JTAG chain and I can upload different VHDL programs to them?  The JTAG header will be located between the CPLDs and the maximum trace length to the devices will be probably 2 inches. Is this too long or will it be alright?

[Altera_Forum]

--- Quote Start ---  I'm implementing a JTAG Daisy Chain for the first time on a PCB.   --- Quote End ---    The device TDO's tri-state after the device is configured. I always put a pull-up on each device's TDO, so that the TDI of the next device is not floating. There's no harm in doing this on the JTAG header too.  Put series resistors on the TDO->TDI chain from the header and between devices. That way if you have trouble with a device, you can remove it from the JTAG chain.  Actually, put series resistors from all the header signals, so that you provide a small amount of ESD protection.   TCK and TMS should be buffered and driven individually to the two devices. You will get transmission line reflections from a daisy chain of a single signal, and depending on layout, one of the devices may see the reflections as double clocks.  Look at this schematic and borrow ideas:  http://www.ovro.caltech.edu/~dwh/carma_board/ http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf  Cheers, Dave

[Altera_Forum]

Understood on the series resistors. I'll go with 50 Ohms. 

 Stupid question: how does a buffer help with reflections? I'll probably go with the same buffer you went with: NC7WZ16P6X. It's quite cheap and tiny.  And if I understood the schematic correctly, I put this between the header and the first CPLD in the chain and the TCK and TMS signals diverge from there on and goes to two CPLDs.  Or perhaps I misunderstood you. Did you mean to say that I should use a buffer per CPLD? I.e.  TCK from header ----> Buffer# 1 ---> CPLD# 1 TCK from header ----> Buffer# 2 ---> CPLD# 2  Same applies to TMS, TDI and TDO on its way back before it enters the header again. I can see how a buffer would help with transmission line effects in this case but not the previous one. The buffer would isolate the signals from each other and so reflections won't be an issue(?).

[Altera_Forum]

--- Quote Start ---   Stupid question: how does a buffer help with reflections? I'll probably go with the same buffer you went with: NC7WZ16P6X. It's quite cheap and tiny.   --- Quote End ---  HDR -> single buffer, and then two series termination resistors on the buffer output to produce two copies of TCK and TMS.  Each of the two series terminated signals will have reflections, but those reflections will occur off the single load at the end of the transmission line. The return reflection will be absorbed by the series termination resistor.    --- Quote Start ---   And if I understood the schematic correctly, I put this between the header and the first CPLD in the chain and the TCK and TMS signals diverge from there on and goes to two CPLDs.   --- Quote End ---  Right, the buffers receive the TCK and TMS signals from the header, and then two copies of each are produced.  I also like to put a buffer on TDI, as a measure of ESD and voltage protection. For the final TDO, its also for ESD protection.    --- Quote Start ---   Or perhaps I misunderstood you. Did you mean to say that I should use a buffer per CPLD? I.e.  TCK from header ----> Buffer# 1 ---> CPLD# 1 TCK from header ----> Buffer# 2 ---> CPLD# 2   --- Quote End ---  There's two ways; a single buffer with dual source termination, or a dual-buffer with two outputs and two series terminations. It depends which TinyLogic buffers you decide to use.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  HDR -> single buffer, and then two series termination resistors on the buffer output to produce two copies of TCK and TMS.  Each of the two series terminated signals will have reflections, but those reflections will occur off the single load at the end of the transmission line. The return reflection will be absorbed by the series termination resistor.  --- Quote End ---    Makes perfect sense now. I can even see where to put the resistors in terms of layout: near the buffer. I'll go with 100 Ohms for this, as your schematic suggests.  It might also be a good idea to put this on the SPI daisy chain.  What book would you recommend for understanding transmission line effects on a PCB?

[Altera_Forum]

--- Quote Start ---  Makes perfect sense now. I can even see where to put the resistors in terms of layout: near the buffer. I'll go with 100 Ohms for this, as your schematic suggests.   --- Quote End ---    The value will be somewhere around 30-ohms. I generally put whatever is the closest part in the BOM for a board. Its not really important to get it right on the first revision of the board. You'll measure it, try a few different values, and settle on the one that looks good.    --- Quote Start ---  It might also be a good idea to put this on the SPI daisy chain.   --- Quote End ---   Its always a good idea to have point-to-point transmission lines when you can.    --- Quote Start ---   What book would you recommend for understanding transmission line effects on a PCB?  --- Quote End ---    I liked the book by Johnson&Graham, "High Speed Digital Design: A Handbook of Black Magic", 1993.   Cheers, Dave

[Altera_Forum]

Thanks. Gonna look up that book now.