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Max V Power Consumption - How to determine toggle rate SIPO/PISO?

Altera_Forum
Honored Contributor II
‎09-21-2011 01:32 PM
1,324 Views

Hello all, 

 

I'm using 3 Max V 240Z for an implementation of a 320 bit serial in parallel out (SIPO) shift register. This shift register will be the driving end of an automotive wiring harness. 

 

At the other end, there will be 3 further Max V 240Z for an implementation of a parallel in serial out shift register. The serial lines will be connected to a MCU. This is the basic overview of a wiring harness tester. 

 

Why use 3 CPLDs when a large BGA package can handle the job? The local industry here cannot solder and inspect BGA packages. So I'm using the next package with the highest I/O - 144-pin TQFP. 

 

I have been researching the power consumption of these CPLDs because I have to choose an appropriate regulator and came across a term called Toggle Rate. I feel I have a basic understanding of this - its how much an output changes dependent on a clock. If the output only changes 1/2 the time, then the toggle rate is simply 50%. 

 

The problem is - how do I estimate this? The SIPO shift register will be loaded with a test vector of walking zeros, so the actual outputs will really only change once and then go back to their "default" state of 1. If my understanding is correct, this will lead to a very low power consumption? 

 

At the receiving end, the PISO shift register, is clocked out via the SPI interface on the MCU. As there are 320 bits at the driving end, the MCU will have to clock out the receiving end 320 x 320 times (= 102400). But again, assuming all the wiring in the harness is point to point (as opposed to one point to many), the same walking zeros test vector will appear on the receiving end. 

 

In reality, the harness will have one-to-many wiring but I don't think it will change the toggle rate that much. 

 

So, here I'm back to square one - how much large of a regulator should I implement for these six CPLDs + MCU? Board space is not an issue. 

 

The MCU is an AVR Mega 128L. I intend to run the CPLDs at 3.3V for VCCIO and of course VCCINT at the standard 1.8V. 

 

Will appreciate any sort of pointers on how to go forward with this.
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Altera_Forum
Honored Contributor II
‎09-21-2011 11:13 PM
664 Views

I have no experience trying to estimate the toggle rates. 

 

What I've always done is to write a realistic test bench, run it in ModelSim recording the VCD file and then use the VCD file for the power analyzer. 

 

http://www.altera.com/support/software/power/sof-qts-power.html
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Altera_Forum
Honored Contributor II
‎09-26-2011 06:40 PM
664 Views

Thanks a lot!

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