Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

Question about top level Entity

Altera_Forum
Honored Contributor II
‎09-26-2011 01:55 PM
1,456 Views

Hi 

 

please, there are some difference between uses of Block Diagra/Schematic File or SOPC builder as top level-entity? 

:(:(
0 Kudos

Link Copied

2 Replies
Altera_Forum
Honored Contributor II
‎09-26-2011 05:18 PM
562 Views

Hi, 

In case of your design will contain extra logic (like a tristate buffer to interface with GMII ethernet for example), You must have a top level entity that contain SOPCBuiler component. 

 

I haven't seen SOPC Builder as top level. 

 

Other users would give more information. 

++
0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎09-26-2011 08:26 PM
562 Views

 

--- Quote Start ---  

Hi, 

In case of your design will contain extra logic (like a tristate buffer to interface with GMII ethernet for example), You must have a top level entity that contain SOPCBuiler component. 

 

I haven't seen SOPC Builder as top level. 

 

Other users would give more information. 

++ 

--- Quote End ---  

 

Thank you frien. 

Alos i use SOPC as top level. But i need to know if there some difference. 

May be there someone that can clarify this.:)
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.