Hello,I have a 4 layer board with Max10 10M08SAU169 (Single Power supply, not using the ADC) device. This is a UBGA package with 0.8mm pitch and I am using several vias, in-between the very small device pads (0.34mm/13.39 mils dia!). Many of the vias are to reach the bottom-side mounted de-coupling caps. I have nearly 20 of these caps! I am using a Switching Adapter (Triad WSU050-2000) as input DC source. This is followed by two LM1117 linear regulators (3.3V and 2.5V) on the PCB. for decoupling caps requirements, i used altera's max10 10m08 eval kit as a reference, however the chip on that kit is a different package. (10M08SAE144C7G, 144 pin EQFP). Further quite likely the Dev kit PCB is likely very different from my own PCB in terms of layers / Vias / Characteristics. I am NOT a PCB layout expert and wonder... 1) If my approach in using the Dev kit as reference for my de-coupling cap strategy is appropriate and sufficient? I am tired of going through different Altera documents (Early power estimation and now PDN doc / XLS sheet...) 2) On the Power plane I have both VCCA (for PLL. Not using the ADC) and bunch of 3.3 V for some of the VCCIO routed together. Any concerns here? Here are additional details.. - Ext Osc of 27 MHz (Temp controlled). PLL is also set to same rate. - GND plane being used. - Ferrite beads used to isolate VCCA and VCCIO and also REFGND from GND Help would be much appreciated! Thanks.
BTW, The EPE spreadsheet after using data from Quartus (size of Logic, RAM, IOs used etc) and entering approximate toggling rate came out with total power consumption of ~ 290mW only.
Most standard MAX10 designs will work well with a single power plane. Placing as much bypass capacitors as possible is a good idea, though. Capacitors directly on the bottom side is a perfect solution, but not necessarily required. You may prefer single side assembly.You are mentioning ADC specific points like isolating REFGND.
Yes, even though I am not using device's ADC, I just added a ferrite bead between REFGND and GND, as suggested in a Board Guideline, another of the several ref docs.. sigh.. :-( Perhaps it' an overkill.1) It's a BGA package. So I was trying to keep the De-coupling caps as close as possible. So using the under side of the device. For future, it's fine if they are on the same side? (and relatively far from the power pins..) 2) So OK to use the Dev kit schematic as a reference, for my de-coupling cap strategy, despite the differences of device packages and PCBs? I was also also wondering if it was possible to just use 2-4 caps per power bank, rather than 1 cap per power pin. Although now I am already using 1 de-coupling per power pin and would just ahead with it. I thought this was also perhaps an overkill? 3) And am I OK with the Linear regulators, though the 5V input would be via a wall mount switching regulator, as mentioned above? Interetingly the Early power Estimation sheet is showing ~ 290mW power consumption, with nearly 200mW in static power only... So the dynamic is only 90mW...? Is the normal.. My clock is only 27MHz and I am using toggle rate of 35%. Device usage is about 50 % LUTs (4050) and 25% FF (2200). 4) Also ok to route VCCA and 3.3V on the same plane? Thanks a lot.
I presume the EPE estimation is correct. Your design should be well with a linear regulator.As mentioned in the pin connection guidelines, VCCA bypassing is particularly relevant for PLL jitter. On the other hand, how much simultaneous switching noise is generated by your FPGA? Depends on the number of active outputs, toggle rate and load. If your design doesn't use PLLs or in jitter sensitive applications, a single 3.3V plane can be well acceptable. Similar problem about number and placement of bypass capacitors. If you did already decide for double side assembly, a bypass capacitor for each power pin is easy to implement, also VCCA ferrite filters. You can do some experiments by providing the components and omitting it later.
Thanks for your input.1) Don't know from where to find out about the 'switching noise generation'. Where is it to be found? Don't see it in the EPE report. My design Is using the PLL, though I VCCA is isolated from VCCIO 3.3V Should I increase the 'spacing' between the VCCA trace and rest of the plane carrying 3.3V VCCIO? Current 'isolation / spacing' for unrelated traces is set to only 16 mils. Also, I am using a 'grid' plane versus a solidly Filled polygon, as the plane. That should be fine? 2) The EPE report is showing about 85mA (3.3V rail) and only 1 mA for 2.5V rail (Very surprised as I am driving bunch of LEDs off this IO bank, albeit very rarely. All 1mA of it is Static and 0mA for Dynamic current..?). A sheet in EPE mentions that for 100mA or over, better to use Switcher supplies. So it seems I am ok with the linear, as you suggested. Thanks,
I tried to run SSN Analyzer, but Quartus is saying "Cannot run SSN analyzer - as the target device does not support it"So I cannot run this SSN Tool on Max10 10M08SAU169 device...? Is there then another way to know about SSN ? Max Clock speed in my design is 27MHz. Is SSN a concern at this speed. Not using any DDRs , Transceivers etc.. Thank you,