Hello everyoneGreetings, I am Ph.D student working on FPGA, I am facing a problem that I couldn't figure out its reason(s). I have implemented SD card reading / writing. The problem I faced , when I try to send more than one value to output, this error displayed : "Error (276003): Cannot convert all sets of registers into RAM megafunctions when creating nodes. The resulting number of registers remaining in design exceeds the number of registers in the device or the number specified by the assignment max_number_of_registers_from_uninferred_rams. This can cause longer compilation time or result in insufficient memory to complete Analysis and Synthesis" The code is process(sclk,sec_no,sec_byte_counter_ram) begin sd_ram((sec_no)*512+sec_byte_counter_ram)<=data_frm_sd; end process; LEDR_READ<=sd_ram(1) ; -- here is the problem instead of no. 1 whatever I added as counter was unacceptable and pop that message, even if counter of 2 integers, unless I used one integer location,then can be read correctly from any location in SD. I would be so thankful for any glance of help since I was in this problem for long time. Best Regards.
The code you posted (without code tags) will not infer a ram, because it does not follow the ram template in any way. It is not synchronous and does not have th required registered address.So when compiling, it tries to build the ram out of logic - and dies when the compiler running out of logic. Given that this is a rather basic mistake, I assume you are an FPGA newbie? have you been through any VHDL tutorials on the subject? I recommended going through digital logic text books as writing VHDL is not at all like writing software.
Dear Tricky, you can name it a gap in knowledge , may be , because I had implemented many circuits before as SDHC, wavelet and VGA... I show the error in this code because it was the same when I used the SRAM in code below .IF (wr_done='0') THEN wr_enable := clk; test <= D(7 DOWNTO 0); A <= std_logic_vector(to_unsigned(i,18)); ELSE test <= D(7 DOWNTO 0); A <= std_logic_vector(to_unsigned(vac,18)); wr_enable := '1'; END IF; nWE <= wr_enable; wdone_test <= wr_enable; --Bidirectional bus:-------------- IF (wr_enable='0') THEN D <= "00000000" & myram(i); ELSE D <= (OTHERS => 'Z'); END IF; END PROCESS; END ARCHITECTURE; here when I replaced myram with SD data I got the same error. And the code above worked well with VGA and images are shown correctly and the ram is created. If I had a problem with basics it wouldn't run eventually. However if you think it is a basic question , I wish you guide me to what to read to pass it. Thank you With my best regards.
This is only a snippet, so I cant really comment on this code - is it synchronous? why are you using variables?The fact you have a variable called "wr_enable" AND a biderectional description using wr_enable, that makes me beleive this is all in the same process - which is poor practice. Did you draw a diagram of your circuit before you did any coding? did you follow the coding guidelines the in the Quartus manual? https://people.ece.cornell.edu/land/courses/ece5760/de1_soc/hdl_style_qts_qii51007.pdf
Dear TrickyThank you for your reply and help, I figured out the problem , there was too many input/out in one clock cycle , I think I was reading and writing in the same time . I will read pdf you sent me . Many thanks .