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I'm working on a schematic with a 10M25DAF256I7G.
I'm going to power the FPGa with supply scheme as stated on Pin Connection Guide Line page 20: VCC: 1.2V VCCINT: 1.2V VCCD_PLL: 1.2V VCCA:2.5V VCCA_ADC:2.5V VCCIO:3.3V I have a problem to understand the JTAG pull-up voltage. As stated on Pin Connection Guide Line: "for configuration voltage of 2.5v, 3.0v or 3.3v, connect this pin through a 10kohm resistor to 2.5v (vccio bank 1 b) to prevent voltage overshoot..." But my VCCIO is 3.3V for all banks. Why it says 2.5V? Furthermore in the MAX10 Configuration User guide on page 3-3 the pull resistor are at VCCIO Bank 1B with clamp diode. So i think i can pull-up to 3.3V. My question is: If i use a configuration scheme as stated on page 20 of the Pin Connection Guide Line, how do i have to connect the jtag pull-up resistor for JTAG signals? Is it 2.5V or 3.3V with diode as stated in the Connection guide line? ThanksLink Copied
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Yes, you can connect the pull-ups to 3.3V.
Refer to the 'max 10 fpga configuration user guide (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/max-10/ug_m10_config.p...)', and figure 3-1 on page 3-3. Pull-ups are tied to VCCIO of bank 1 or 1B, depending on device. Cheers, Alex
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