I am looking for the possibility to interface a Gbit ethernet IC with four input and four output DDR lines. I am reading the Max10 documentation and i was not able to figure out if this is possible. There are notes on DDR memory interface IP in Quartus, but i was not able to instantiate a DDR input or output primitive.
Is there no list of primitives for the Max10 family so someone could look and see what hardware is available and instantiate it?
I assume there is no IDDR or ODDR hardwrae block inside the Max10. Can i run the interface at 250 MHz and "simulate" a 125 MHz DDR interface and expect to meet the timing?
Probably you can use the DDIO_IN and DDIO_OUT as shown in figure 14/15 of the MAX10 GPIO UG - https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_gpio.pdf#p...
To meet the timing, the proper way is to run quartus full compilation and chek is the timing analysis is clean.
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Thank you for your suggestion. I was able to test a simple example of DDR input/output using the IP wizard. I connect the clock to PLL which was set to source synchronous mode.
Can you please help me me one more thing about that. I would actually prefer using the direct hardware instantiation without the wizard. Is this not possible with Max10 (or other intel fpga devices)? I am missing the hdl library guide for Max10 device - something similar to Xilinx UG953 for instance.
I don't think it is possible for hardware instantiation without using the wizard.
Perhaps, you can create a new thread for new question, so that it can route to a correct person accordingly to the specific technical area. Thanks for your understanding.