Max10 power consumption with and without PLL

[designEngineer]

I have a design where power is a big concern. When running the power estimate originally I ended up with the following results (snippets from the power report):

+--------------------------------------------------------- ; Thermal Power Dissipation by Block Type +---------------------+----------------------------------- ; Block Type ; Total Thermal Power by Block Type +---------------------+----------------------------------- ; PLL ; 9.92 mW ; Combinational cell ; 0.13 mW ; Clock control block ; 0.71 mW ; Register cell ; 0.45 mW ; I/O ; 0.47 mW +---------------------+-----------------------------------+------------------------------------------------------------------------------------------------- ; Current Drawn from Voltage Supplies Summary +----------------+-------------------------+---------------------------+-------------------------- ; Voltage Supply ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) +----------------+-------------------------+---------------------------+-------------------------- ; VCC ; 5.09 mA ; 1.13 mA ; 3.96 mA ; VCCIO ; 1.93 mA ; 0.09 mA ; 1.84 mA ; VCCA ; 16.11 mA ; 1.83 mA ; 14.29 mA ; VCCD_PLL ; 8.97 mA ; 4.46 mA ; 4.51 mA ; VCCINT ; 0.08 mA ; 0.00 mA ; 0.08 mA ; VCCA_ADC ; 0.00 mA ; 0.00 mA ; 0.00 mA +----------------+-------------------------+---------------------------+--------------------------

Through some online research I found that VCCA is mostly supplying the PLL. In order to reduce power consumption I removed the PLL from the design (I can supply the clocks needed externally) and re-ran the power estimate with the following results (same code snippets):

+--------------------------------------------------------- ; Thermal Power Dissipation by Block Type +---------------------+----------------------------------- ; Block Type ; Total Thermal Power by Block Type +---------------------+----------------------------------- ; Combinational cell ; 0.12 mW ; Clock control block ; 0.80 mW ; Register cell ; 0.42 mW ; I/O ; 0.40 mW +---------------------+-----------------------------------

The 9.92 mW for the PLL is gone, so this is good and expected. However on the next section:

+------------------------------------------------------------------------------------------------- ; Current Drawn from Voltage Supplies Summary +----------------+-------------------------+---------------------------+-------------------------- ; Voltage Supply ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) +----------------+-------------------------+---------------------------+-------------------------- ; VCC ; 5.14 mA ; 1.18 mA ; 3.96 mA ; VCCIO ; 1.91 mA ; 0.07 mA ; 1.84 mA ; VCCA ; 11.99 mA ; 0.00 mA ; 11.99 mA ; VCCD_PLL ; 4.09 mA ; 0.00 mA ; 4.09 mA ; VCCINT ; 0.08 mA ; 0.00 mA ; 0.08 mA ; VCCA_ADC ; 0.00 mA ; 0.00 mA ; 0.00 mA +----------------+-------------------------+---------------------------+--------------------------

VCCA is still drawing significant static current (11.99 mA) and VCCD_PLL is also still drawing static current (4.09 mA).

My main questions are:

1. What else (other than the PLLs) is VCCA supplying to have such current draw?
2. When there is no PLL in the design whatsoever, why is VCCD_PLL still drawing 4.09 mA static power?
3. Rather than just not using a PLL in the design, is there maybe a way to completely disable the FPGA's PLL feature in order to reduce the static power consumption?

Thank you for your help!

[Rahul_S_Intel1]

Hi, Kindly find the inline answers 1. What else (other than the PLLs) is VCCA supplying to have such current draw? >> It is the power to PLL and ADC block and have to connect to power supply even PLL and ADC are not in use reference page no: 15 https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/max-10/pcg-01018.pdf 2. When there is no PLL in the design whatsoever, why is VCCD_PLL still drawing 4.09 mA static power? >> As per the architecture of Max 10 FPGA the module will draw the current even PLL is not using and you cannot left this pin unconnected from power supply 3. Rather than just not using a PLL in the design, is there maybe a way to completely disable the FPGA's PLL feature in order to reduce the static power consumption? >> No, you have to provide the supply as per the recommendation from Max 10 Pin connection guidelines