In a Max10 10M02SCE144I7G I have a variable frequency input signal from 0Hz to about 80kHz.
On that signal I apply a digital filter to remove the glitches (without changing the frequency with a gloabl clock of 3.8684Mhz) and I make it go out.
However, by applying a 50000Hz signal, the output signal has a frequency of 52631Hz. Even removing the filter and sending the input signal to the output nothing change.
Looking at the signal with the oscilloscope there are no apparent differences other than the delay of the output signal with respect to the input, but also the oscilloscope (besides the frequency meter on the output) tells me the difference of the two frequencies.
Are you trying to say, that by connecting the input to output directly still your are not getting expected output??
Check the pin assignment and probe it, In the correct location on your board.
Exactly yes by connecting the input to the output I am not getting the expected output.
I got a slight improvement by removing the "schmitt trigger" setting from the input pin.
Today I have been busy with other things, but tomorrow I will try to set the maximum current to the output pin, at the moment it is set to 3.3V LVTTL with minimum current.
You need to listen to Anand and check your pin assignments first. You've got something fundamentally wrong that has nothing to do with schmitt triggers or current drive. Also, is your digital scope aliasing and giving you a false reading?
You have to probe exactly the Output of FPGA,
If you probe the signal after it passes through an active or passive component you will see the difference.
Also check the pin assignments.
I checked the assignment, but in my projects all the I/O pins have a specific function, these 4 pins perform the filter of a frequency signal and the output signal is incorrect, but analyzing it with the oscilloscope what appears is rather a distortion due to the delay on the fronts that deceives the frequency meter.
What kind of assignments you refer to? Phisical pins, specific property?
4 pins because the signals to be filtered are two different, but my tests are aimed at only one channel, the other is off. Also the other MAX10 functions are off.
Can't understand what are you trying to convey?
Share your project.
Here an extract from the project:
entity speed_input is
generic( board_code : integer :=16#C1#);
--Gemini II bus signals
B_CLK : in std_logic; --Bus clock
Data : inout std_logic_vector(15 downto 8);--Bus data
Addr : in std_logic_vector(15 downto 0);--Address of internal registers
--Speed input board specific signals.
Speeding0_sig : in std_logic; --Input from speed transducer 0.
Speeding1_sig : in std_logic; --Input from speed transducer 1.
SS0_Out_Filt : out std_logic;--Filtered Speeding0_sig
SS1_Out_Filt : out std_logic;--Filtered Speeding1_sig
enable : in std_logic); --enable slot decoder
SS0_Out_Filt <= Speeding0_sig;
SS1_Out_Filt <= Speeding1_sig;
In Speeding0_sig signal is the input and SS0_Out_Filt the output.
What I see is that the output signal is slightly behind the input signal, but this is normal.
What is not correct, however, is that the output frequency is a little higher than the input frequency (measured with the frequency meter).
Error on the signal fronts?
If you have connected the input to output without any logical operations, You have to see the same signal with the same frequency.
If you are seeing different signals.