Max10 vccio power sequence

[fra29]

Hi,

I want to use a Max10 FPGA (10M04DAF256) with two different VccIO voltages: 3.3V and 1.8V.

The issue is that the 3.3V and 1.8V power supplies will not ramp at the same time.

Banks 1B and 8 will be powered by 3.3V at the same time as the VCC, VCCINT, VCCA, VCCD_PLL.

But Bank 3 and 4 will be powered later (can be up to 1 second later) by 1.8V.

Will the Max10 be configured and operational (enter user mode) on its banks 1B and 8 in the mean time ? (i.e. in the interval of time between the apparition of the 3.3V and the apparition of the 1.8V)

Thank you.

[AminT_Intel]

Hello, 

Yes they will enter the user mode if that is how you designed it. You can refer to page 28 of this document for detailed explanation of configuration sequence for Intel Max 10 devices from this link: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf

Thank you,

Amin

[fra29]

Hello Amin,

Thank you for your answer concerning the user mode.

Is it safe for the device to have some of its IO banks powered seconds after VCC, VCCINT, VCCA, VCCD_PLL, VCCIO8, VCCIO1B ?

Best regards

[AminT_Intel · Accepted solution]

Hello,

Yes that will be okay.

Thanks