I am new in designing FPGA. I have a very simple question, on MAX 10, there are high speed and low speed io pins. My question is does the clock pins on low speed io pins bank have less accuracy than the one on high speed io pins banks?
I'm not sure your question is clear. The 'accuracy' depends on quality of the clock you supply the FPGA. This isn't a function of whether you use a clock pin in a high or low speed I/O bank.
