Maximum Load of a DPCLK Pin of the MAX10

[Altera_Forum]

What is the maximum capacitive load which can be powered by a DPCLK output of a Max 10 Device? 

I want to use a 10M08SCE144C8G to power 4 ADC clock inputs with a capacitve load of 5pf for each ADC with a frequence up to 20MHz. Is the maximum current equal to normal I/Os?  Thanks for your help

[Altera_Forum]

can you try to do a complete compilation and see if it passes?

[Altera_Forum]

I'm pretty sure Altera don't publish maximum loads. They only state performance figures based on particular loads - in the case of MAX 10, typically 5pf. 

 What I/O standard are you looking to drive? DPCLK won't let you drive certain differential signaling standards from it. In that respect it is no different to any other general purpose I/O pin. The DPCLK pins are intended to be used as a low latency control routes in to the device. If you're looking for higher performing clock output pins, look to the PLL_L_CLKOUT pins with lower latency from the PLLs.  Finally, I suspect you should be able to run a 20pF load at 20MHz. Just be careful with your routing if that's split over four destinations.  Cheers, Alex

[Altera_Forum]

You can also try to perform IBIS model simulation to check if with that specific loading, can the toggling rate still meet your requirement or not.

[Altera_Forum]

You can download the Max 10 ibis model at https://www.altera.com/support/support-resources/download/board-layout-test/ibis/ibs-ibis_index.html

[Altera_Forum]

Thanks for your quick response :-) 

 I want to drive the Clk Inputs of the ADC on a Single-Ended 3.3V CMOS Level. I think i´ll use the PPL_L_CLKOUT Pin to drive an external clock buffer, just to make sure that i wont get any problems with my clock signals