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Hi,
what is a maximum frequency applicable to different class of Nios II processor, considering that the other logics on FPGA does not contains critical path ?Link Copied
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It depends on which part and speed grade you are using. For a rough estimate, check out this document from Altera:
nios ii performance benchmarks (http://www.altera.com/literature/ds/ds_nios2_perf.pdf)- Mark as New
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It depends on your requirement.
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The fMAX you will get will also depend on the number of peripherals and the structure of the Avalon bus, because the Avalon bus arbitration can become a bottleneck if you are not careful. You can speed things up by putting non-performance critical peripherals behind a bridge. I think there is discussion of this at the end of the Nios II Handbook.
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I think around 100MHz in a Cyclone III.
But it indeed depends a lot on your system. Faster is possible... Also consider that not only the clock speed determines the system speed. If you have your off-chip memory (for example DDR) at a differetn clock speed, you can end up with a bottleneck to the memory due to clock domain crossing issues. Benchmarks are always generated using the fastest possible speed grade of components, with only use of on-chip RAM (possible only connected to a tightly coupled interface), and sometimes with some compiler tricks to get some higher numbers in the reports. Stefaan
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