Hello,
I have this small ROM design, which now has increased to 16k and I had to start using the Mega wizard plugin manager to generate the rom (and so use the block ram).
My board is the DE1 (Cyclone II).
However, this generated rom has some kind of problem, I think it must be a basic problem and I would like to ask if you guys see some trivial error in this procedure that I am missing.
The rom data is read from a .mif file.
The rom design that works is this:
entity rom is
port(
clock : in std_logic;
address : in std_logic_vector(15 downto 0);
q : out std_logic_vector(7 downto 0)
);
end rom;
architecture rtl of rom is
begin
process (clock)
begin
if clock'event and clock = '1' then
case address is
when x"0000" => q <= x"21";
when x"0001" => q <= x"00";
Can a 1-port ROM generated by the megawizard replace the above design ?
