Can I use a normal pin as DDR2 controller's DQ?

[Altera_Forum]

I make a mistake when I do the schmatics work, so I must use a normal pin as DDR2 controller's DQ. 

When I complie the project, I face the error: altmemphy pin placement unsuccessful.The assigned location PIN C20 for DQ pin "DDR_DQ[6]" is  not a legal location. The DDR2 controller is generated by the QuartusII. Can I fix the error by doing some setting of QuartusII? Or I must  re-layout the PCB? Thank you!

[Altera_Forum]

The DDR2 controller is required to use DQ/DQS groups according to the assignments in device pinout files. Unfortunately you have to change the layout.

[Altera_Forum]

Stratix family? If you look through the handbook, the hardware has specially structures on the DQS ports that are used by the PHY. If it used "generic" FPGA structures, it would never meet timing.

[Altera_Forum]

--- Quote Start ---  Stratix family? If you look through the handbook, the hardware has specially structures on the DQS ports that are used by the PHY. If it used "generic" FPGA structures, it would never meet timing.  --- Quote End ---    Not quite, in Cyclone II, III or IV timing is met using the "generic" fabric. Maximum speed is of course lower than for Stratix with the DDR registers built in to the IO-ring.

[Altera_Forum]

I'm not quite sure, which specific hardware resources are provided for dedicated DQ and DQS pins in Cyclone devices. But they use specific pins, which was the question of the original poster.

[Altera_Forum]

Thank you everyone! I use Cyclone III in this project.I will check the handbook of Cyclone III.