Memory Interface Cyclone 3

[Altera_Forum]

I am wondering what the fastest memory interface would be for the cyclone three. 

 Q1. What is the fastest RAM chip supported by altera IP or that works with cyclone 3? Q2. What is the fastest single cycle ram chip that can be used with cyclone 3?  Correct me if I am wrong, from my reading I have found that   1. the Cyclone III LS FPGA dev kit has has the fastest memory interfaces for cyclone3 supported by altera...  IS61VPS51236A-250B3 is the fastest SSRAM chip for cyclone 3... "The SSRAM device consists of a single standard synchronous SRAM, providing 2 Mbyte with a 36-bit data bus. This device is part of the shared FSM bus which connects to the flash memory, SRAM, and MAX II CPLD EPM2210 System Controller. The device speed is 200 MHz single-data-rate. There is no minimum speed for this device. The theoretical bandwidth of this 32-bit memory interface is 6.4 Gbps for continuous bursts. The read latency for any address is two clocks, in which at 200 MHz, the latency is 10 ns and at 50 MHz, the latency is 40 ns. The write latency is one clock." from devkit docs  MT47H32M16HR-3:F is the fastest DDR2 chip for cyclone 3... "There are two DDR2 devices, providing 512 Mbit of memory each for a total of 1024 Mbit of on-board DDR2 SDRAM. Each device interface has a 16-bit data bus, which can be configured to run individually or together as a 32-bit data bus. One of the device is pinned out to FPGA bank 7 and a second device is pinned out to FPGA bank 8. These memory interfaces are designed to run at a maximum fequency of 167 MHz for a maximum theoretical bandwidth of over 10.6 Gbps. The internal bus in the FPGA is typically 2 or 4 times the width at full rate or half rate respectively. For example, a 167 MHz 16-bit interface will become a 83.5 MHz 64-bit bus." from dev kit docs  2. It seems that the latency is an issue with all the ram chips. So my second question was if any body knows of any single cycle ram chips with no clock cycle latency...like you put the address on the bus on rising edge of clock, the ram then outputs the data at that address on the falling edge of the clock. I am having some issues finding this...even the name of it would be good to know, but a particular chip would be even better.  I am just interested in this due to the simplicity of the operation to make it easier to think about while working with the memory interface  I know that the ddr2 above has 4 times the speed of the state method here...considering it can transfer 4 data elements per clock, but the latency is an issue for random memory queries...It is not as big of an issue for burst data writes. Anyways any help/confirmation of these statements is appreciated thanks.

[Altera_Forum]

I think the closest you will find is something called ZBT SRAM, or Zero-Bus-Turnaround Synchronous SRAM. It's likely this has the lowest latency of all memories. 

 If you are looking at something that is more DDR-like have a look at RLDRAM (Reduced Latency DRAM). I think Micron is about the only company still making the stuff.  Generally speaking, all DRAM are optimized for burst-type operation and generally really struggle with random accesses or r-w / w-r operations. The controller is also a big factor in this. SSRAM is better in this regard but sustained throughput and clock frequencies are commonly far less than their dynamic cousins.  Stephen

[Altera_Forum]

Even ZBT rams have several cycles of latency. The one we use has a 2 cycle latency, but is able to do one operation per clock cycle.

[Altera_Forum]

ZBT just reduces the read/write turnaround, not the pipeline latency. 

 As said, there is a natural compromise between latency and throughput. You must decide which one is more important for you. For smaller latency you may want flow-through SSRAM. This would give you one cycle read latency.  If you really want just half cycle latency, then you would need to use async SRAM, or either use a PLL to double (or even just delay) the external clock. Either way, you probably would need to reduce the clock frequency.