Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21588 Discussions

Jtag configuration for ARRIA GX

Altera_Forum
Honored Contributor II
‎08-14-2010 10:43 AM
1,106 Views

hi all........ 

We have some problem related to JTAG configuration.The problem is .... 

When all the bank are given 3.3 v supply the jtag working fine but when bank 4 and bank 7  

are given 1.5 v( for HSTL logic) supply then fpga is not detecting jtag.Whenever we give supply 1.5v to bank 4 then jtag is not working since TDO pin power from bank 4. please suggest some solution since 1.5v must for our design in bank4.
0 Kudos

Link Copied

2 Replies
Altera_Forum
Honored Contributor II
‎08-14-2010 12:07 PM
424 Views

I guess, you need a level translating buffer for TDO. Altera programming adapters are sufficient slow to tolerate 10 or 20 ns of additional delay.

0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎08-17-2010 04:06 AM
424 Views

plz suggest some reference circuit or level translator.

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.