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Jtag configuration for ARRIA GX

Altera_Forum
Honored Contributor II
‎08-14-2010 10:43 AM
1,135 Views

hi all........ 

We have some problem related to JTAG configuration.The problem is .... 

When all the bank are given 3.3 v supply the jtag working fine but when bank 4 and bank 7  

are given 1.5 v( for HSTL logic) supply then fpga is not detecting jtag.Whenever we give supply 1.5v to bank 4 then jtag is not working since TDO pin power from bank 4. please suggest some solution since 1.5v must for our design in bank4.
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Altera_Forum
Honored Contributor II
‎08-14-2010 12:07 PM
453 Views

I guess, you need a level translating buffer for TDO. Altera programming adapters are sufficient slow to tolerate 10 or 20 ns of additional delay.

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Altera_Forum
Honored Contributor II
‎08-17-2010 04:06 AM
453 Views

plz suggest some reference circuit or level translator.

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