Memory Layout for Video Frames (D5M Camera + VGA)

[Altera_Forum]

Hi. I'm working on the implementation of an object detection algorithm using NIOS on the DE1. My next step is to get the D5M camera interfaced and be able to display the processed output on a VGA. I'm currently looking at the DE2 D5M_Video_In example and am somewhat confused about the part where a Video DMA is used to store the pixel data from stream to memory. The frame resolution used is 640x240 with a 16 bit RGB format. In the Video IP Cores for DE Series Boards document, the subsection 3.1 Memory Layout for Video Frames shows that 32 bits are reserved per pixel (even if some are unused) in both addressing formats. However the DE2 only has 512KB of SRAM and the image size used would require 600KB if it really is 32 bits per pixel. Is there a mistake in my understanding? 

 On a side note the algorithm requires 8 bit gray scale pixels and I would like to be able to keep the image as large as possible. I want to retrieve the pixel data and process it via NIOS. I'd appreciate any advice on the matter. Hopefully this part of the forum is more active than the UP section :).  Ammar

[Altera_Forum]

My Guess for 16 bit RGB it's storing the data either in 565 format (most likely) or 1555 format. 

 565 = 5 bits Red, 6 bits Green, 5 bits Blue in a 16 bit word. 1555 = 1 bit Alpha (or used) 5 bits each for Red/Green/Blue.  565 is more commonly used, since the human eye is more sensitive to Green.  Pete

[Altera_Forum]

Hey. Thanks for the reply. According to the doc they use 565 for 16 bit RGB and 4444 for RGBA. The thing that's confusing me is whether the packet size remains the same. I've attached the relevant pdf (I'm talking about pages 7-10). I'm starting to think that I'm making a silly mistake and the addressing is 32 bits but the data packet depends on the color space. 

 Ammar

[Altera_Forum]

Hi Ammar: 

 Yes.. In the past I've always used the Concecutive Address method. If you look at figure 10. The data width is variable (k-1:0) where k in your case would be 15 bits.  This is also implied in Figure 9, where your addressing for 16 bit data is 2 byte aligned (LSB of address = 0) and for 32 bit data is 4 byte aligned (two LSB's of address = 0)  Pete

[Altera_Forum]

Oh I think I understand now. However, shouldn't the data width be k:0 instead of k-1:0 ? Thanks for all the help! 

 Ammar