I am working on updating a PCB board schematic, and migrating from Arria 10 to Stratix 10. Some questions that I have now:
Some pins seen on Arria 10 (like DEV_OE, DEV_CLRN, CRC_ERROR, ASDO, NCE, and NIO_PULLUP) can not be found on Stratix 10. What should I do? Can I simply remove connections to these pins in old design? Thanks,
Thank you for reaching out to Intel FPGA Community.
For your information, migration pin support is available for the same device family within the same package.
You may refer to this Migration Pinout - Intel Communities