Designing a LVDS receiver (4 channels, deserialization factor = 8, Clock Input = 100MHz, Data Rate = 800Mbps) in Cyclone IV E device EP4CE40F23C6 does not meet the timing requirement in the Fast 1200mV 0c model in TimeQuest. The LVDS receiver generates a 400MHz (2.500 ns) clock but the minimum clock period is restricted to 2.899 ns in the Fast 1200mV 0c model in TimeQuest. Therefore 'minimum pulse width violation' is reported.
My question is why there is this restriction. According to the datasheet the maximum LVDS clock frequency for Cyclone IV E C6 device can be 437.5MHz (2.286ns). So why is the minimum clock period in the fast timing model restricted to 2.899ns?
Any help would be highly appreciated.
