Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

process to include a text file in vhdl testbench

Altera_Forum
Honored Contributor II
1,044 Views

sir, 

 

i want to include a text file in my testbench code. but i don't understand how to include this?? i come to know to include  

"use std.textio.all; 

use IEEE.std_logic_textio.all;" 

should i have to decare this package manually??? plz help me.:cry:
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
349 Views

thats all you need to include. But remember you cannot compile a testbench in quartus. You can only run it in modeslim. Textio does not work in quartus.

0 Kudos
Reply