Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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More info needed regarding Schmitt Trigger input setting in Max-V CPLD

griffin1701
初学者
734 次查看

I am looking for the center voltage value for a pin on the Max V CPLD, when it is configured as a 3.3V Schmitt trigger input.  The datasheet shows a hysteresis voltage of 400 mV for Vccio = 3.3V, but it does not specify that actual trip points, or at least the center point.

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AqidAyman_Intel
577 次查看

Thank you for the input, Frank.


Do you have any more help needed on this issue?


在原帖中查看解决方案

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FvM
名誉分销商 II
673 次查看

Hi,

unfortunately MAX V datasheet (neither other CPLD or FPFA datasheets) give typical threshold voltage for 3.3V IO-standard, you can assume that it's somewhere between Vil,max of 0.8 V and Vih,min of 1.7 V. 3.3V ST thresholds have in case of doubt +/- offset to lvcmos33.

To evaluate typical ST thresholds, you'll need to make your own measurements. You can e.g. setup a slow RC ST oscillator and measure reversal points.

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griffin1701
初学者
619 次查看

Thanks for the info.  We decided to perform the measurements ourselves, as you recommended.

 

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AqidAyman_Intel
578 次查看

Thank you for the input, Frank.


Do you have any more help needed on this issue?


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AqidAyman_Intel
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I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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