Mulitple MSI support in Cyclone IV - IP Compiler for PCI Express

[SSmit7]

Hi there

I would like to implement multiple MSI using the IP compiler for PCIe, with the target device being a Cyclone IV. 

I have successfully managed to do this already with a Cyclone V (using the Cyclone V Hard IP for PCIe), but the IP compiler for the Cyclone IV does not appear to be able to export the same signals.

Is anyone aware of whether it is possible to implement multiple MSI on the Cyclone IV, and if so, how does one go about doing so. 

Thanks in advance.

Kind regards,

SS

[KhaiChein_Y_Intel]

Hi,

May I know the device part number for Cyclone IV and Cyclone V that you are using? What is the Quartus version?

Thanks

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

I choose a random OPN for Cyclone IV, the MSI capability is available.

Thanks

Best regards,

KhaiY

[SSmit7]

Hello there

Thank you for the reply.

I should have been clearer: We are using a EP4CGX30CF23I7N. This device requires a soft-ip implementation. The FPGA is intended to be the endpoint, with a processor acting as the root-port. Additionally, we require an Avalon-MM interface, where the IP compiler that you show seems to require an Avalon-ST implementation. Specifically, we are implementing it in Qsys (Quartus 13.0.1). Is this possible to implement multiple MSI in that configuration?

Regards,

SS

[KhaiChein_Y_Intel]

Hi SS,

The MSI export option was added in the later version of the Intel Quartus Prime software.

You may upgrade the software version to v20.1

Thanks

Best regards,

KhaiY

[SSmit7]

Hello

I have upgraded to version 20.1.1 and though I can see the export option, this does not provide me with the same number of options as the Cyclone V export. I have already looked at these options and there is no clarity if it is possible to use multiple MSI in this way. Please do not close the thread.

Regards,

SS

[KhaiChein_Y_Intel]

Hi,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best regards,

KhaiY

[SSmit7]

Hello

Please do not close the thread, I do not feel that my questions have been adequately addressed. I need to know if I can use multiple MSI on the Cyclone IV using the Avalon-MM interface in Qsys if I export the interface, and if this is possible, could you provide guidance on how to do it. Thank you.

Regards,

SS

[KhaiChein_Y_Intel]

Hi,

You may refer to the doc below:

IP Compiler for PCI Express User Guide https://static6.arrow.com/aropdfconversion/87ae7171f324fca79ad75c9c3f6b13d10e0e88c9/ug_pci_express.pdf

Cyclone V Hard IP for PCI Express User Guide

https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/ug/ug_c5_pcie.pdf

Thanks

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best regards,

KhaiY