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Altera_Forum
Honored Contributor I
1,189 Views

Multistage pipelined multiplexer

Hello, 

 

My design has to switch between four - 128 bit wide buses. 

Using a simple coded mux (even with registered inputs and outputs) causes Fmax to drop to unacceptable levels. 

 

I'm thinking to use a multistage pipelined MUX. I.E: the input buses will themselves be broken into smaller pipelined segments.  

Does the IP catalog provide such a component ? Can the LPM_MUX be configured in such a way ?
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3 Replies
Altera_Forum
Honored Contributor I
128 Views

 

--- Quote Start ---  

 

I'm thinking to use a multistage pipelined MUX 

 

--- Quote End ---  

 

Good thinking ... I've already written one for you ... 

 

Download the code from Post#5 

http://www.alteraforum.com/forum/showthread.php?t=41601 

 

View the PDF to understand the construction of the mux. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
128 Views

Thanks! 

 

Do you know if Altera has a similar component ?
Altera_Forum
Honored Contributor I
128 Views

 

--- Quote Start ---  

 

Do you know if Altera has a similar component ? 

--- Quote End ---  

 

Probably not. Personally I like to have HDL code for useful components, rather than use a vendor black-box. The pipelined mux will map directly into 4-LUT or 6-LUT FPGA architectures - just set the parameters correctly. 

 

Cheers, 

Dave
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