My confuse about the Cyclone IV GX transceiver.

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

My confuse about the Cyclone IV GX transceiver.

1,046 Views

I want use the EP4CGX15F14 to implement 2 1000BASE-X ethernet.

But I am confuse about the clock networks.The EP4CGX15F14 has only one transceiver block GXBL0,There are 2 channels in the block.

My understanding is that the 2 rx channel use the CDR respective, the 2 tx channel use 2 MPLLs in the FPGA.So I should feed 2 reference clocks to the

pins.

Is it right?

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.