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Valued Contributor III
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My confuse about the Cyclone IV GX transceiver.

I want use the EP4CGX15F14 to implement 2 1000BASE-X ethernet. 

But I am confuse about the clock networks.The EP4CGX15F14 has only one transceiver block GXBL0,There are 2 channels in the block. 

My understanding is that the 2 rx channel use the CDR respective, the 2 tx channel use 2 MPLLs in the FPGA.So I should feed 2 reference clocks to the  

pins. 

Is it right?
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