My first project with Altera and Quartus: FSK modulator/demodulator

[Altera_Forum]

Hi ! 

 Today I started one small project to create one FSK (modulator and demodulator). In the next photo you can see the SCH of my modulator. The output are updated in every falling CLK of the slow frequency to ensure one duty cycle of the 50%.  I have never studied VHDL, but I think it may be faster to use VHDL to do a schematic design. Someone could translate the schema to code VHDL? Somebody know a great site online to learn VHDL?  Can someone give me an idea of how to design the demodulator?    http://img13.imageshack.us/img13/6980/schfsk.jpg (http://img13.imageshack.us/my.php?image=schfsk.jpg)     http://img60.imageshack.us/img60/1201/simulatorfsk.jpg (http://img60.imageshack.us/my.php?image=simulatorfsk.jpg)   (http://img60.imageshack.us/my.php?image=simulatorfsk.jpg)

[Altera_Forum]

i don't see your schematic picture.

[Altera_Forum]

nevermind, it appeared later. 

 some of the code here may help you learn VHDL. i have never tried to port something directly from 7400 series to VHDL, but a direct port may not be as elegant as VHDL solution. counters and registers are very easy and flexible:  http://esd.cs.ucr.edu/labs/tutorial/