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I have a NIOS II progressing currently running on a DECA development board.
I have the TSE IP running and an application based of the SimpleSocketServer. It has been extended to send and received UDP packets in additional threads.
This works fine, on receipt of a "Subscribe" packet, it sends a "Ping" packet every second. This is my basic test functionality.
The FPGA also has a custom IP block that includes a Interrupt Sender interface, triggered (ultimately) by an encoder.
When the ISR is hit, the TSE code stops working an repeatedly sends a "no free buffers for rx" message. Are there any requirements on interrupts required for TSE to work?
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Addendum:
Previously it only started to fail when I ran the motor (i.e. ~100000 interrupts per second). It was now failing immediately. This was due to me editing out code to find the error and I had edited out the line that cleared the interrupt. (Now fixed that).
Without the motor running, it now fails after some thousands of interrupts (over many seconds - I am turning the rotor by hand).
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May I know which document you followed?
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Finding documentation has been a struggle with this project.
There seems a lack of "how to" with explanation. There are examples which do not explain themselves at all. There is deep documentation that goes into details far more than a "user" of an IP block should need.
So... which documentation? I have built up sufficient "know how" from the spectrum of docs in order to get a design that works. No single document.
This was posted three weeks ago, so I have moved on somewhat. The design is working most of the time, but I am not 100% sure that this error did not appear while I was testing on Friday. The error message is fairly obtuse and diagnosing is not simple. So any advice on its meaning/cause would be useful.
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May be you can try to increase the internal FIFO depth.
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