NIOS II Simulation Error

Altera_Forum · ‎08-13-2013

Hi again.

I have a simple system with Nios II e, SDRAM, On-Chip memory, JTAG-UART and Sys-ID Peripheral. I created "Hello World" in the NIos II Eclipse IDE and it runs, I get "Hello from Nios II!" in the Nios II Console. When I start the simulation with Modelsim, I become errors in two locations in the testbench code.

First:

 process (clk, reset_n)
    VARIABLE write_line6 : line;
    begin
      if reset_n = '0' then
      elsif clk'event and clk = '1' then
        if std_logic'((W_valid AND R_wr_dst_reg)) = '1' then 
          if is_x(R_dst_regnum) then 
            write(write_line6, now);
            write(write_line6, string'(": "));
            write(write_line6, string'("ERROR: cpu_0_test_bench/R_dst_regnum is 'x'"));
            write(output, write_line6.all & CR);
            deallocate (write_line6);
            assert false report "VHDL STOP" severity failure;
          end if;
        end if;
      end if;
    end process;

And second:

 process (clk, reset_n)
    VARIABLE write_line13 : line;
    begin
      if reset_n = '0' then
      elsif clk'event and clk = '1' then
        if std_logic'((i_read AND NOT i_waitrequest)) = '1' then 
          if is_x(i_readdata) then 
            write(write_line13, now);
            write(write_line13, string'(": "));
            write(write_line13, string'("ERROR: cpu_0_test_bench/i_readdata is 'x'"));
            write(output, write_line13.all & CR);
            deallocate (write_line13);
            assert false report "VHDL STOP" severity failure;
          end if;
        end if;
      end if;
    end process;

I dont what i did wrong, actually I buid a system as in the Lights and Using the SDRAM tutorials from Altera, just without the LEDs and Switches. Can someone help me? I just dont know why I get this errors.

Regards.

Altera_Forum · ‎08-14-2013

It seems that the CPU model is getting some X signals at one point, so check that everything is connected and initialized correctly in your test bench. You can check what the CPU is receiving back on its Avalon masters. In a VHDL simulator an uninitialised register is set to the value 'U', which can then become 'X' when combined with other signals.

Altera_Forum · ‎08-17-2013

Ok, thank you, Daixiwen, got it now. Seems like there is something wrong with SDRAM testbench model. If I link all data (.bss, .text, .heap.....) to the on-chip memory, simulation runs.

What do i need to do to simulate SDRAM? I work with SOPC-Builder and VHDL. Tutorials I found were in Qsys and Verilog, so it was not realy helpfull.

So I turned on "Include a functional memory model in the system testbench" in the SDRAM properties in SOPC-Builder and regenerated the system. Also I turned on "enable_sim_optimize" in BSP-Editor options (NIOS II SBT for Eclipse).

In Modelsim, after 's' -> 'w' -> 'run 5ms' I get

# ************************************************************

# This testbench includes an SOPC Builder Generated Altera model:

# 'sdram_0_test_component.vhd', to simulate accesses to SDRAM.

# Initial contents are loaded from the file: 'sdram_0.dat'.

# ************************************************************

.....seems to be right I think.

But in the waveform the signals az_addr and az_data are X all the time. za_data is Z after reset, 0 during the reset.

Do I have to wire up something? I'm realy new with all this stuff and to work through the generated code, I will need realy long time. Would be nice, if someone could help or give me a hint.

Thank you!

Altera_Forum · ‎08-20-2013

I've never used the SDRAM model so I don't know how it is supposed to work.

How is your SPU reset vector set?

what signals do you have on the input of the SDRAM controller?

Do you really need to simulate with an SDRAM?