NIOS Program store in DDR3 UNIPHY hanging when writing reading from other MPFE port

Altera_Forum · ‎09-18-2014

I'm using the DDR3 controller as my program store for the NIOS. I have two ports set up in the DDR3 controller with port 0 (the NIOS port) given priority. The second port is connected to a write and read master from the mSGDMA block (writing and reading video data).

I have proven the mSGDMA is working using another DDR3 controller and separate DDR3 chip. However, I'd like to get rid of the second DDR3 so would like to share the first DDR3 with the NIOS program code.

When the mSGDMA is connected to the second port, the NIOS comes up perfectly but once the NIOS sets the mSGDMA reading and writing to the DDR3 the NIOS hangs. I have signal tapped and the mSGDMA is writing and reading correctly so it does get started. So it seems that once the mSGDMA has started, the NIOS cannot get access to the program code anymore.

I would have thought this couldnt be the case because I have set the NIOS port on the DDR3 controller to a higher priority.

Could anyone suggest why the NIOS is not getting access through it's higher priority port? Qsys image attached

Update: A few theories

1. The MPFE does not support bursting (have tried to rule out)

2. The mSGDMA is in park mode so never gives the DDR3 controller a chance to release control to the NIOS

3. The MPFE will not work as the NIOS program store and the NIOS cannot tolerate the delays involved (Even when set to higher priority)

I have also set up the mSGDMA to transfer 16KB three times and not repeat. Therefore the NIOS has complete control after these three writes. But it still hangs, suggesting it cannot tolerate any interruption to it's program store.

Any thoughts appreciated

Altera_Forum · ‎09-23-2014

Just an update. I have a couple of running theories, if anyone could rule any out that would be great. I've been studying a reference design (http://www.alterawiki.com/wiki/reference_design_-_cyclone_v_hard_memory_controller_with_avalon_mm_data_width_expanded_for_user_ecc) and cannot see anything I have set up differently.

1. The MPFE will not work as the program store for the NIOS

2. The MPFE does not support bursting (Currently set to 64 bursts, though have tried disabling bursting)

3. The MPFE does not work with bidirectional ports (Have tried second (non NIOS) ports as in reference design to read and write but to no avail)

4. Due to the way the mSGDMA works, it never stops writing/reading to surrender control to the NIOS. I have edited it to continuously loop back on its descriptors so the chain never ends.

I've tried to rule out 1 - 3 already, but am running out of ideas.

Altera_Forum · ‎09-23-2014

Just an update. I have been studying a reference design (http://www.alterawiki.com/wiki/reference_design_-_cyclone_v_hard_memory_controller_with_avalon_mm_data_width_expanded_for_user_ecc) but cannot see any differences in setup except that the reference design is not trying to use the DDR3 for the NIOS program store. I have a few running theories that I would appreciate if anyone could rule out.

1. The MPFE will not work for the NIOS program code store.

2. The MPFE does not work for bidirectional ports (Have attempted to rule out by separating the mSGDMA read and write ports as in reference design but no help)

3. The mSGDMA is constantly reading and writing and is never surrendering control to the NIOS. The mSGDMA writes and reads in park mode so is constantly writing and reading.

4. The MPFE does not support bursting (Have tried to rule out by disabling bursting and by reducing bursts from 64 to 4)

Appreciate any thoughts, I'm running out of ideas