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NIOS is generating Read Signal Twice.

Altera_Forum
Honored Contributor II
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Hi, 

 

There is a custom interface of NIOS with a device, having own DSP-Processor. Interface is 16-bit data bus. While reading the data NIOS is generating CSn and RD Enable twice. 

 

Please help me to resolve this problem. 

 

-- 

Regards, 

Chander
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Altera_Forum
Honored Contributor II
988 Views

Hello, 

what about bus width mismatch? A 32 bit read can turn in two 16 bit reads to consecutive addresses.
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Altera_Forum
Honored Contributor II
988 Views

Read Write both are 16 bit.

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Altera_Forum
Honored Contributor II
988 Views

So, Nios 2 has a 32 bit read/write port (one for read and one for write) while your device has an interface with 16 bits on the avalon bus. This is a mismatch, the interconnect fabric in SOPC builder will split the read or the write in two. Take a look at http://www.altera.com/literature/manual/mnl_avalon_spec.pdf, paragraph 3.6.1 

 

 

--- Quote Start ---  

 

For example, when a 32-bit master port 

performs a read transfer from a 16-bit slave port, the system interconnect fabric 

executes two read transfers on the slave side on consecutive addresses, and presents 

32-bits of slave data back to the master port 

 

--- Quote End ---  

 

 

If I understood correctly your situation, this may be a good cause for reading twice.
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Altera_Forum
Honored Contributor II
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Hi, 

this is a flaw in the SOPC builder. The NIOS data master is a 32 Bit master. So accesses are always 32 bit, even if you do a 16 bit access. With 8 bit components it is even worse. The first or seond access to your 16 bit component (depending on the address) will have both byte enables disabled.
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Altera_Forum
Honored Contributor II
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Not a flaw. It is declared in the Avalon Interface Specifications. Look my previous post.

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Altera_Forum
Honored Contributor II
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The misunderstanding is related to the fact that NIOS always performs 32bit read accesses, even if you explicitly use IORD_16DIRECT or IORD_8DIRECT: in these cases you'll always get multiple CS and RD strobes. 

This can be annoying if your external address is a fifo or some register which is supposed to change at every read access. 

The solution I used in a similar case is using a 32bit external data bus and connecting only the 8 or 16 bits I need; this way I always perform a single 32bit access and discard extra bits.
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Altera_Forum
Honored Contributor II
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Gabrigob you are right. But for me this is a flaw. Why executing two 16 bit transfers when only 16 bits are needed ? And one of the accesses is an "empty" access with byte enables disabeld. This increases access times unnecessarily.

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Altera_Forum
Honored Contributor II
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Hi, Cris, 

 

Thanks for your kind information, my issue get resolved. I took 32 bit bus from NIOS and mapped the Lower 16 bit with custom interface. 

 

Thanks a lot to all replies. 

 

 

--- Quote Start ---  

The misunderstanding is related to the fact that NIOS always performs 32bit read accesses, even if you explicitly use IORD_16DIRECT or IORD_8DIRECT: in these cases you'll always get multiple CS and RD strobes. 

This can be annoying if your external address is a fifo or some register which is supposed to change at every read access. 

The solution I used in a similar case is using a 32bit external data bus and connecting only the 8 or 16 bits I need; this way I always perform a single 32bit access and discard extra bits. 

--- Quote End ---  

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