NIOSII using the FPGA-to-HPS SDRAM Bridge via Address Span Extender

[Altera_Forum]

Hello, 

 I want to share my DDR3-RAM from HPS with my NIOS2 on the FPGA. In hps instantiation I configured an Avalon MM Bidirectional port with 64bit width (FPGA-HPS-SDRAM Bridge). Afterwards I used the address span extender to reduce the 4GB hps in a smaller window of 256MB. I choose 32bit for Datapath width and configured the windows to the sizes. I export the windowed slave to an upper level. The name of the exported extender is appl_subsystem_DDR3_RAM_to_FPGA.   In the other subsystem I have NIOSII with an absolute reset vector set to 0x4000 0000. There I located a Avalon MM Pipeline which I use to export to upper level again. The size of the bridge is 32/8/30 bytes to interact, so the bridge is located from 0x4000 0000 to 0x3fff ffff.  Now I connect the address span extender to the pipeline bridge on the top level. Everything is generated fine and also compilation works fine.  But when I want to create BSP in NIOS2 EDS I get following error:  SEVERE: CPU "cpu1" reset memory "appl_subsystem_DDR3_Ram_to_FPGA" has no matching memory region.   WARNING: Tcl script "bsp-set-defaults.tcl " error: CPU "cpu1" reset memory "appl_subsystem_DDR3_Ram_to_FPGA" has no matching memory region.   SEVERE: [Error] altera_hal_linkerx_generator: Required linker section mappings do not exist: "[.entry, .exceptions, .rodata, .rwdata, .text, .bss, .heap, .stack]"  SEVERE: [Error] altera_hal_linkerx_generator: Required linker section mappings do not exist: "[.entry, .exceptions, .rodata, .rwdata, .text, .bss, .heap, .stack]"  SEVERE: nios2-bsp-create-settings failed.  nios2-bsp: nios2-bsp-create-settings failed   Thanks for your replies

[Altera_Forum]

--- Quote Start ---  Hello,  I want to share my DDR3-RAM from HPS with my NIOS2 on the FPGA. In hps instantiation I configured an Avalon MM Bidirectional port with 64bit width (FPGA-HPS-SDRAM Bridge). Afterwards I used the address span extender to reduce the 4GB hps in a smaller window of 256MB. I choose 32bit for Datapath width and configured the windows to the sizes. I export the windowed slave to an upper level. The name of the exported extender is appl_subsystem_DDR3_RAM_to_FPGA.   In the other subsystem I have NIOSII with an absolute reset vector set to 0x4000 0000. There I located a Avalon MM Pipeline which I use to export to upper level again. The size of the bridge is 32/8/30 bytes to interact, so the bridge is located from 0x4000 0000 to 0x3fff ffff.  Now I connect the address span extender to the pipeline bridge on the top level. Everything is generated fine and also compilation works fine.  But when I want to create BSP in NIOS2 EDS I get following error:  SEVERE: CPU "cpu1" reset memory "appl_subsystem_DDR3_Ram_to_FPGA" has no matching memory region.   WARNING: Tcl script "bsp-set-defaults.tcl " error: CPU "cpu1" reset memory "appl_subsystem_DDR3_Ram_to_FPGA" has no matching memory region.   SEVERE: [Error] altera_hal_linkerx_generator: Required linker section mappings do not exist: "[.entry, .exceptions, .rodata, .rwdata, .text, .bss, .heap, .stack]"  SEVERE: [Error] altera_hal_linkerx_generator: Required linker section mappings do not exist: "[.entry, .exceptions, .rodata, .rwdata, .text, .bss, .heap, .stack]"  SEVERE: nios2-bsp-create-settings failed.  nios2-bsp: nios2-bsp-create-settings failed   Thanks for your replies  --- Quote End ---     Hello all, I also has the same issue. Did you solved this. Anyone please advise.

[Altera_Forum]

--- Quote Start ---  Hello all, I also has the same issue. Did you solved this. Anyone please advise.  --- Quote End ---    http://www.niosii.net/support/kdb/solutions/rd03182014_17.html  With friendly regards  Chris

[Altera_Forum]

Hi, 

 I had the same problem before, and got this answer from Altera:  Due to a limitation in Qsys we cannot currently dynamically set the Address Span expander to be / not be visible as memory for the NIOS II. This issue is planning to be release in to ACDS 14.1. However, please note that this schedule is not commitment.  As for now, our suggested workaround is to remove# characters from line 546 and line 551 of "altera_address_span_extender_hw.tcl" file located at "<install_dir>/ip/altera/merlin/altera_address_span_extender" as below. • set_interface_assignment windowed_slave embeddedsw.configuration.isMemoryDevice 1 • set_interface_assignment windowed_slave embeddedsw.configuration.affectsTransactionsOnMasters "expanded_master"   But there is another way to solve the problem:  Change the embeddedsw.configuration.isMemoryDevice to 1 for the extender, the only penalty is that you have to do THIS every rebuild of the qsys-system and the previous is fix one time...  I hope this helps...