Necessity of pin OSC_CLK_1 in 1ST280EU2F50I2VG FPGA

[Ankit_Srivastava]

Why exactly do we need OSC_CLK_1 pin in 1ST280EU2F50I2VG FPGA when we can use it from System Clock as well ? Which specific section/Tile does it take care of ?

[RichardTanSY_Intel]

You may checkout the User Guide below:

https://www.intel.com/content/www/us/en/docs/programmable/683762/22-1/configuration-pin-differences-from-previous.html

Hope that explain your questions.

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.

[RichardTanSY_Intel]

Hi,

May I know does my latest reply answered your question?

[Ankit_Srivastava]

Yes, I got my required answer. Thanks Richard for support.

[RichardTanSY_Intel]

Thanks for acknowledge the solution provided. 

 I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.