Need help for LVDS deserializer

[Altera_Forum]

Hello, 

I need to interface an ADC from Maxim (MAX1437) which have LVDS output (clock, frame, an 12 bits data wide) with a MAX10 FPGA. The goal is to deserialize data's.  I develop from Quartus II, and I saw MegaWizard Function like Alt_Pll, Alt_LVDS but it's not very easy to use for beginner like me. And it's not an evidence to know how link my ADC signals with FPGA. Do I have to do the job with clock or frame signal ?  If anyone can help and guide me ?  Thanks

[Altera_Forum]

You need to use the 'Altera Soft LVDS' IP. Refer to the 'soft deserializer' section, in the 'max 10 lvds receiver design' chapter, of the "max 10 high-speed lvds i/o user guide (https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0cb8qfjaaahukewjdqy69spfjahucqxokhs1ucea&url=https%3a%2f%2fwww.altera.com%2fliterature%2fhb%2fmax-10%2fug_m10_lvds.pdf&usg=afqjcnedbunwv-hclbcgzblt7-uhz7h8yg&bvm=bv.107467506,d.d24)".  

 Search for 'LVDS' in the IP catalog search in Quartus to start configuring the IP. Set it up for 'RX' only, set your data and clock rates. I suggest you use a 'SERDES factor' of 6 (as 12 isn't available). This will give you half of the result every 6 'VCLKOUT' cycles.  Ensure the VCLKOUTP/N signals connect to dedicated clock pins on the FPGA. Connect VOUTP/N to a suitable P/N pin pair. Configure your FPGA pin assignments for LVDS.  Cheers, Alex

[Altera_Forum]

Hello, 

I did exactly what you advised me. I configured Altera Soft LVDS with SERDES factor of 6 and with internal PLL first to begin. Because I'm using Altera MAX10 Evaluation kit, I planned to choose pins 52 and 50 (differential pair LVDS) for "input frame" (that is PLL input signal).  But, after compilation, I has error message like that :"Error (176554): Can't place PLL -- I/O "input frame" pin I (port type INCLK of the PLL) is assigned to a location which is not connected to port type INCLK of any PLL on the device".  So, I did another compilation without assignment pin directive for this signal, and Quartus fitter allocated input signal on pins 28 and 27.  I've not tested it yet, but, do you know if PLL input signal will not be able allocate any I/O LVDS pin ?  Best regards,

[Altera_Forum]

Hi, 

 I believe you are referring to PLL reference clock of the LVDS instance. The refclk need to be placed to dedicated clock input pin but not normal LVDS IO pin.

[Altera_Forum]

Hello, 

I developed an intermediate project that consist to deserialize data only on even bit. This one is correct when I simulate it in functional mode. But the datas on outputs device are not valid that is confirmed by Signal Tap software. I would like run gate-level simulation to understand where is the problem but no sdf file are generated during compilation. So, is there any restriction to do this under Quartus II 15.0 with MAX10 devices ? Thanks, Stéphane

[Altera_Forum]

Think you can double check on the signal integrity at the output pin also to see if there is any issue.

[Altera_Forum]

Do you observe any timing violation or marginal passing in TimeQuest?