Need help : implement Gigabit Ethernet

[Altera_Forum]

Hello, 

I'm new on this forum, so I hope that I'll be clear with my question. I'm currently working on Cyclone III FPGA Development Kit with the EP3C120F780C7N.  For my project I have to etablish a communication between my PC and my board with the Gigabit Ethernet. I have to send to the board datas to configure a camera and then send the pixels to the PC for a display. My PHY device is Marvell 88E1111 so I try since two weeks to configure it with RGMII interface. My problem is that I don't know how to use the TripleSpeedEthernet 9.1 either with MegaWizard Plug-In Manager (how to link all the I/O) or with SOPC (where I'm a total beginner). Can someone help me and explain me how to use these functions or how to begin (maybe a tutorial exists with v9.1sp1) to advance in my project ? Thanks in advance.

[Altera_Forum]

It can be anyone of those, the PHY chip if capable of swithcing the TX/RX lines if necessary. 

Did you try to find the packets with signalTap?

[Altera_Forum]

so now i have tried with both, and still without success  

about signaltap, i can't use it because a problem of licence   here is what the console displays me :   nios2-terminal: connected to hardware target using JTAG UART on cable nios2-terminal: "USB-Blaster [USB-0]", device 1, instance 0 nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)  =============== Software License Reminder ================ This software project uses an unlicensed version of the NicheStack TCP/IP Network Stack - Nios II Edition. If you want to ship resulting object code in your product, you must purchase a license for this software from Altera. For information go to: "http://www.altera.com/nichestack" ===================================================== InterNiche Portable TCP/IP, v3.1   Copyright 1996-2008 by InterNiche Technologies. All rights reserved.  prep_tse_mac 0 Your Ethernet MAC address is 00:07:ed:ff:3b:14 prepped 1 interface, initializing... [tse_mac_init] INFO : TSE MAC 0 found at address 0x10022800 INFO : PHY Marvell 88E1111 found at PHY address 0x12 of MAC Group[0] INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0] INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... INFO : PHY[0.0] - Auto-Negotiation PASSED INFO : PHY[0.0] - Checking link... INFO : PHY[0.0] - Link established INFO : PHY[0.0] - Speed = 1000, Duplex = Full OK, x=0, CMD_CONFIG=0x00000000  MAC post-initialization: CMD_CONFIG=0x0400020b [tse_sgdma_read_init] RX descriptor chain desc (1 depth) created mctest init called IP address of et1 : 192.168.1.234 Created "Inet main" task (Prio: 2) Created "clock tick" task (Prio: 3) DHCP timed out, going back to default IP address(es)  Simple Socket Server starting up [sss_task] Simple Socket Server listening on port 30 Created "simple socket server" task (Prio: 4)   then i tried a ping to 192.168.1.234 : unsuccessfull or telnet 192.168.1.234 30 : unsuccessfull   any idea is welcome thanks for your help 

[Altera_Forum]

You can try and debug the software and put breakpoints in the TCP/IP stack to find out what is happening but it will be more difficult than using signaltap in my opinion. 

What license problems do you have? If it is just because of the Opencore evaluation window, you can start the Quartus programmer as a separate application instead of configuring the FPGA directly from Qaurtus. That way you can keep the Opencore window open and run Signaltap from Quartus.

[Altera_Forum]

ok ty, i'll try tis today 

yesterday night i found something and tried it but it was impossible to compile the programm the link is :  http://www.altera.com/support/kdb/solutions/rd11122009_293.html

[Altera_Forum]

about the licence, the messige is this one : 

"Can't open Signal Tap II Logic Analyzer. Verify that the licence file exists and is stored in the correct location. If you are using Quartus II Web Edition Software, you must turn on the Talkback feature to use the Signal Tap II Logic Analyzer." about my licence, i get one from altera and followed all the step to use it when i try to enable signal tap, i have to choose a signal tap file, of course i haven't got one because i can't create a new one due to the previous message in the info box, and before i have turned on the talkback feature

[Altera_Forum]

hinanotabu86  

Maybe it would be easy to implement send and receive functions on MAC level? All you need is TSE+it's components. Besides I have workable drivers for rx\tx and i can attach it here.

[Altera_Forum]

Maybe it would be easy to implement send and receive functions on MAC level? 

-> What do you mean exactly ? I understand that : a send function for my pixel / a receive function for the register configuration. And by function, you mean add sopc component link to tse_mac or source file for simple socket server ?   All you need is TSE+it's components.  -> Which components ? SGDMA-Tx and SGDMA-Rx ? or some others ?   Besides I have workable drivers for rx\tx and i can attach it here. -> i think that will help me a lot for understanding and reach my goal   thanks a lot for your response

[Altera_Forum]

I never had this message from SignalTap... do you have the web edition? In that case, can you enable Talkback as they suggest?

[Altera_Forum]

i fixed the problem with signal tap, i tried to watch all the signals in relation with ethernet but : 

1) i have to recompile the design and that generate me a ...time_limited.sof, the one which is related with my .stp 2) when i run as -> nios 2 hardware with nios II 9.1 IDE after program the time-limited.sof that leave me the target processor pausing  OR i run the .sof then run as -> niosII hardware without problem but with incompatibility with teh .stp for moment, i will take time to improve myself with sopc and soft (i.e. write on the lcd) before make new tests next week if you have any advice, it will be very helpfull, thanks

[Altera_Forum]

When you configure a FPGA with a time limited sof file, you'll have an alert box telling you that you are in Opencore evaluation mode. It is very important not to close that window! If you do the CPU will stop working. That's why I suggested to launch the Quartus programmer as a separate application, so that you can use SignalTap even if you have a time limited sof file.

[Altera_Forum]

hi all,  

first thanks for your help, especially daixi now the design for GbEth is working well, but I have now idea how i can continue i try to send 8bit every 40 ns from a camera but i absolutly don't know how to do that, first i erased the component i don't need (as led, switch ...) but i always get an error about a multiple fan-out for ddr's data now i'll try to add to the current design something for sending my byte (my pixels values) to the pc  any ideas will be welcome, thanks in advance

[Altera_Forum]

hi dim99, 

 I am interested in your workable drivers for send/rcv on MAC level, could you please attach here?  Thanks,    --- Quote Start ---  hinanotabu86  Maybe it would be easy to implement send and receive functions on MAC level? All you need is TSE+it's components. Besides I have workable drivers for rx\tx and i can attach it here.  --- Quote End ---  

[Altera_Forum]

hi 

i began from zero to do my own architecture i've successfully write on a character lcd, and use different pio for controling some vhdl functions around to count some frame and display the count value in the lcd now, i would like to control a memory to store pixels values inside and then make the nios processor able to read these values i heard about the dma but haven't yet understtod how to use for controling an external memory as a SRAM one any idea how to do ?

[Altera_Forum]

can someone answer me this question please : 

when i create an array in Nios II IDE, where is this array ? i mean which part of my board store this array : onchip_memory ? the program memory ? the read-only data memory ? the read/write data memory ? the heap memory ? or the stack memory ? thanks for any answers

[Altera_Forum]

Please create a new thread. Your questions have nothing to do with the original topic.

[Altera_Forum]

Hi all, 

 I have the problem with ping. I connect PC with DE3 board Terasic with straith cabel and I can't ping. Do I need crossover cabel ?? All is ok I use Simple socket server and simple benchmark application ,100 Mbps link full duplex established.    Could someone send me working drivers for that.   It is very important for me becouse it is end study project.   Thanks very much   dex85 (at) o2 (dot) pl